• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of Digital Contents Society
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• v.2 no.1
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• pp.51-61
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• 2001

The FLC(Fuzzy Logic Controller) is stronger to the disturbance and has the excellent characteristic to the overshoot of the initialized value than the classical controller, and also can carry out the proper control being out of all relation to the mathematical model and parameter value of the system. But it has the restriction which can't adopt the environment changes of the control system because of generating the fuzzy control rule through an expert's experience and the fixed value of the once determined control rule, and also can't converge correctly to the desired value because of haying the minute error of the controller output value. Now there are many suggested methods to eliminate the minute error, we also suggest the GA-FNNIC(Genetic Algorithm Fuzzy Neural Network Intelligence Controller) combined FLC with NN(Neural Network) and GA(Genetic Algorithm). In this paper, we compare the suggested GA-FNNIC with FLC and analyze the output characteristics, convergence speed, overshoot and rising time. Finally we show that the GA-FNNIC converge correctly to the desirable value without any error.

• Journal of the Korea Society of Computer and Information
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• v.18 no.1
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• pp.11-19
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• 2013

For an autonomous multi-mobile robot system, path planning and collision avoidance are important functions used to perform a given task collaboratively and cooperatively. This study considers these important and challenging problems. The proposed approach is based on a potential field method and fuzzy logic system. First, a global path planner selects the paths of the robots that minimize the cost function from each robot to its own target using a potential field. Then, a local path planner modifies the path and orientation from the global planner to avoid collisions with static and dynamic obstacles using a fuzzy logic system. In this paper, each robot independently selects its destination and considers other robots as dynamic obstacles, and there is no need to predict the motion of obstacles. This process continues until the corresponding target of each robot is found. To test this method, an autonomous multi-mobile robot simulator (AMMRS) is developed, and both simulation-based and experimental results are given. The results show that the path planning and collision avoidance strategies are effective and useful for multi-mobile robot systems.

• ETRI Journal
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• v.35 no.3
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• pp.448-458
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• 2013

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1012-1015
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.179-184
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• 2010

The digital substation automation system has contributed hugely to increasing the stability of power systems by providing not only protection and control of power systems but diagnostic features alongside them. Digital substation automation systems in the scale of substations consist of integrated operation systems and intelligent electronic devices. The main intelligent electronic devices currently in use are digital protection relays and the bay controllers in Gas insulated switchgears. Proficiently accomplishing the coordination of protection within the power system as a means of ensuring reliability and contriving for the stability of power supply through connection of function, the application of bay controllers is crucial, which collectively manage the protection relay at the bay level in order to achieve both. In this research, the bay controllers to be used in high-voltage Gas insulated switchgear has been localized, and in particular, the logic function and editor required in order to minimize the complicated hardware-like cable connections in the local panel have been developed. In addition, to ensure the strength and reliability of the bay controller hardware developed herein, the type tests from KERI have been successfully completed.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

• Journal of The Korean Astronomical Society
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• v.29 no.spc1
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• pp.389-390
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• 1996

The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.66.1-66.1
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• 2012

Although all printed cost-less radio frequency identification (RFID) tags have been considered as a core tool for bringing up a ubiquitous society, the difficulties in integrating thin film transistors (TFTs), diodes and capacitors on plastic foils using a single in-line printing method nullify their roles for the realization of the ubiquitous society1,2. To prove the concept of all printed cost-less RFID tag, the practical degree of the integration of those devices on the plastic foils should be successfully printed to demonstrate multi bit RFID tag. The tag contains key device units such as 13.56 MHz modulating TFT, digital logic gates and 13.56 MHz rectifier to generate and transfer multi bit digital codes via a wireless communication (13.56 MHz). However, those key devices have never been integrated on the plastic foils using printing method yet because the electrical fluctuation of fully printed TFTs and diodes on plastic foils could not be controlled to show the function of desired devices. In this work, fully gravure printing process in printing 13.56 MHz operated 32 bit RFID tags on plastic foils has been demonstrated for the first time to prove all printed RFID tags on plastic foils can wirelessly generate and transfer 32 bit digital codes using the radio frequency of 13.56 MHz. This result proved that the electrical fluctuations of printed TFTs and diodes on plastic foils should be controlled in the range of maximum 20% to properly operate 32 bit RFID tags.