• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.4
• /
• pp.71-76
• /
• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.101-104
• /
• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Proceedings of the IEEK Conference
• /
• 2000.06e
• /
• pp.183-186
• /
• 2000

In this paper we propose a new architecture of a programmable digital automatic gain controller(AGC) for analog interface in mixed mode systems. Compared with conventional analog AGCs which have difficulties in integration due to large capacitors, the proposed AGC is easily integrated. So the production cost can be reduced. In addition, The proposed AGC has a better performance in temperature, and power supply variations, and substrate noise than analog counterparts do. To prevent erroneous operations of the AGC due to noise, a mal-function preventer is newly proposed. In addition, to achieve an optimized AGC time constant, we propose a logic block which controls an up-down counting clock. This is directly related to the changing speed of the AGC gain. Implemented with a 0.25 $\mu\textrm{m}$ 1-poly, 5-metal CMOS parameters, the AGC operates from a single 2.5V power supply with the dynamic range of 36.ldB and occupies active area of 500$\mu\textrm{m}$${\times}$600$\mu\textrm{m}$

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.31-37
• /
• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.413-416
• /
• 1998

Sensitivity and calibration considerations are most important in the design and implementation of real control systems. Ideally parameter changes due to various causes should not appreciably affect the system's performances. But all the values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. In this paper, we propose a digital controller which has the capability of calibration and gain adjustment as well as the execution of control law. Specifically the problems of gain adjustment and offset calibration in the light source and CdS sensor module for position measurement in a flexible link system are considerably resolved. The parameters of measurement module are prone to change due to environmental brightness conditions resulting in poor steady state performance of the overall control system. Thus a proper method is necessary to provide correction to the changed values of gain and offset in the position measurement module. The proposed controller, whenever necessary, measures the open-loop characteristics, andthen calculates the offset and sensor gain correction values based on the prepared standard measurements. It is applied to the control of a flexible link system with the gain and offset calibration porblems in the light sensor module for position to show the applicability.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
• /
• v.3 no.2
• /
• pp.5-10
• /
• 2004

In this paper, the hybrid-type current controller for inverter TIG systems was implemented and it was shown that the low-current pulse wave forms with high dynamic performance could be obtained. It is not sri easy to obtain the optimum gain tuning of PID controllers in digital PWM control methods. Hybrid control methods which uses automatic tuning techniques after adding fuzzy control methods to traditional PID controllers are chosen to improve the dynamic performance of PID controller's. To demonstrate the practical significance and dynamic performance improvement of the results, some simulation and experimental results are presented.

• Journal of the Korea Computer Industry Society
• /
• v.3 no.1
• /
• pp.27-34
• /
• 2002

There is much interest on information communications owing to the rapid development of network and IT(Information Technology). Analog signals are converted into digital signals for information communications. However, it is very difficult to completely erase the distortion induced during the conversion of analog signals such as voices and images into digital signals. Existing audio graphic equalizer requires very complex processes to calculate the gain and coefficients of the higher-order filter which is required to generate natural sound and to satisfy the need of each person. Unfortunately it is uneconomical and very difficult to embed the existing digital audio equalizer in the system because of the complexity of the existing digital audio equalizer for high quality sound. This paper discusses the design of a new digital audio graphic equalizer(DAGEQ) which can improve system performance and the quality of audio sound, and can be embedded in the system. This new DAGEQ is designed so that the gain can be controlled automatically. The automatic control of coefficients and gain empowers real time processing and the improvement of audio quality.

• Journal of Power Electronics
• /
• v.19 no.4
• /
• pp.1000-1010
• /
• 2019

The use of internal-model-based linear controller, such as resonant controller, is a well-established technique for the current control of grid-connected systems. Attractive properties for resonant controllers include their two-sequence tracking ability, the simple control structure, and the reduced computational burden. However, in the case of continuous-designed resonant controller, the transient performance is inevitably degraded at a low switching frequency. Moreover, available design methods for resonant controller is not able to realize the direct design of transient performances, and the anticipated transient performance is mainly achieved through trial and error. To address these problems, the zero-order-hold (ZOH) characteristic and inherent time delay in digital control systems are considered comprehensively in the design, and a corresponding hold-equivalent discrete model of the grid-connected converter is then established. The relationship between the placement of closed-loop poles and the corresponding transient performance is comprehensively investigated to realize the direct mapping relationship between the control gain and the transient response time. For the benefit of automatic tuning and real-time adaption, analytical expressions for controller gains are derived in detail using the required transient response time and system parameters. Simulation and experimental results demonstrate the validity of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.4
• /
• pp.18-26
• /
• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.58-67
• /
• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.