• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.875-881
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• 2007

This study explores the attention effects of PPL(product placement) in multimedia contents. PPL has been attracted attention in multimedia as well as marketing communication field as a beneficiary model. For the research, multimedia screen is divided into 9 sections and the serial 9 digit($1{\sim}9$) is assigned to the each part of the screen. The visual exposure forms of each 9 digit are composed by 2-dimension(2D) and 3-dimension(3D). And the visual exposure patterns of each 9 digit are consisted of stopping and moving image. As a result, the 5th quartering has been proved the most attracted attention regardless of all exposure forms including 2D/3D and slopping/moving image. This means center of the multimedia screen is the best place for PPL. Especially in one digit moving screen the attention of the digit has reached the climax. This suggests moving PPL is able to get more attention than stopping. These results provide the most effective PPL position in the screen of the multimedia and PPL's visual exposure forms for maximizing multimedia user's attention. Finally, these findings can be a guideline fer message arrangements of the multimedia screen.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.15-26
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• 2005

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.695-698
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• 2005

The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.12
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• pp.1923-1930
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• 2004

This paper presents digital microflow controllers(DMFC), where a fluidic digital-to-analog converter(DAC) is used to achieve high-linearity, fine-level flow control for applications to precision biomedical dosing systems. The fluidic DAC, composed of binary-weighted flow resistance, controls the flow-rate based on the ratio of the flow resistance to achieve high-precision flow-rate control. The binary-weighted flow resistance has been specified by a serial or a parallel connection of an identical flow resistor to improve the linearity of the flow-rate control, thereby making the flow-resistance ratio insensitive to the size uncertainty in flow resistors due to micromachining errors. We have designed and fabricated three different types of 4-digit DMFC: Prototype S and P are composed of the serial and the parallel combinations of an identical flow resistor, while Prototype V is based on the width-varied flow resistors. In the experimental study, we perform a static test for DMFC at the forward and backward flow conditions as well as a dynamic tests at pulsating flow conditions. The fabricated DMFC shows the nonlinearity of 5.0% and the flow-rate levels of 16(2$^{N}$) for the digital control of 4(N) valves. Among the 4-digit DMFC fabricated with micromachining errors, Prototypes S and P show 27.2% and 27.6% of the flow-rate deviation measured from Prototype V, respectively; thus verifying that Prototypes S and P are less sensitive to the micromachining error than Prototype V.V.

• Journal of the Korean Society of Physical Medicine
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• v.8 no.2
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• pp.281-287
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• 2013

PURPOSE: The study was designed to investigate the effects of visual, auditory, and visuoauditory cues on simple Serial Task Performance in heaithy adults. METHODS: Sixty-three right-handed heaithy adults without history of neurological dysfunction were participated. A modified version of the Serial Reaction Time Task (SRTT) using five blocks of perceptual motor sequences was administered. The blocked paradigm consisted of the five blocks with randomly repeated 8 digit sequences with 5 repetition. Three types of sensory cue were employed: visual cue, auditory cue and visuoauditory cue. All subjects were assigned to press the matched botton as quickly and accurately as possible, when one of 8 stimulations was presented(one, two, three, four, five, six, seven, eight). The reaction time, accuracy, and P300 latency were measured during serial task performance. The mean reaction time(ms), accuracy(%), and P300 latency(ms) were compared between three types of cue using ANOVA. RESULTS: The reaction time to auditory cue was significantly longer than visual and visuoauditory cues(p<.001). And accuracy to auditory cue was significantly lower than visual and visuoauditory cues(p<.001). All P300 latency(at Fz, Cz, Pz) were significantly longer than to visual and visuoauditory cues(p<.05). CONCLUSION: It is suggested that type of cues influence in choice reaction. These data may helpful in designing not only effective motor learning training programs for healthy persons but also reeducation programs for patients with neurological dysfunction.

• Journal of Korean Neurosurgical Society
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• v.47 no.3
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• pp.191-198
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• 2010

Objective : This study is planned to determine the neurocognitive difficulties of hydrocephalic adults. Methods : The research group contained healthy adults (control group, n : 15), and hydrocephalic adults (n : 15). Hydrocephalic group consisted of patients with idiopathic aquaduct stenosis and post-meningitis hydrocephalus. All patients were followed with shunted hydrocephalus and not gone to shunt revision during last two years. They were chosen from either asymptomatic or had only minor symptoms without motor and sensorineural deficit. A neuropsychological test battery (Raven Standart Progressive Matrices, Bender-Gestalt Test, Cancellation Test, Clock Drawing Test, Facial Recognition Test, Line Orientation Test, Serial Digit Learning Test, Stroop Color Word Interference Test-TBAG Form, Verbal Fluency Test, Verbal Fluency Test, Visual-Aural Digit Span Test-B) was applied to all groups. Results : Neuropsychological assessment of hydrocephalic patients demonstrated that they had poor performance on visual, semantic and working memory, visuoconstructive and frontal functions, reading, attention, motor coordination and executive function of parietal lobe which related with complex and perseverative behaviour. Eventually, these patients had significant impairment on the neurocognitive functions of their frontal, parietal and temporal lobes. On the other hand, the statistical analyses performed on demographic data showed that the aetiology of the hydrocephalus, age, sex and localization of the shunt (frontal or posterior parietal) did not affect the test results. Conclusion : This prospective study showed that adult patients with hydrocephalus have serious neuropsychological problems which might be directly caused by the hydrocephalus; and these problems may cause serious adaptive difficulties in their social, cultural, behavioral and academic life.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.871-880
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• 1993

Conventional binary addition rules require a carry formation and propagation to the most significant bit, and lead to serial addition. Thus, the carry progapation in a binary addition stands as a hindrance to the full utilization of parallelism optics offers, Optical adders using a modified signed-digit(MSD) number system have been proposed to eliminate the carry propagation chain states to represent the three possible digits of MSD number system must encode three different states to represent the three possible digits of MSD. In the paper, we propose the design of a parallel optical adder based on 2-bit addition rules using the method of symbolic substitution(SS).

• Sleep Medicine and Psychophysiology
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• v.12 no.2
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• pp.122-132
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• 2005

Objectives: The objective of this study is to assess cognitive functions and their relationship with sleep symptoms in young narcoleptic patients. Methods: Eighteen young narcolepsy patients and 18 normal controls (age: 17-35 years old) were recruited. All narcolepsy patients had HLA $DQB_1$ *0602 allele and cataplexy. Several important areas of cognition were assessed by a battery of neuropsychological tests consisting of 13 tests: executive functions (e.g. cognitive set shifting, inhibition, and selective attention) through Wisconsin card sorting test, Trail Making A/B, Stroop test, Ruff test, Digit Symbol, Controlled Oral Word Association and Boston Naming Test; alertness and sustained attention through paced auditory serial addition test; verbal/nonverbal short-term memory and working memory through Digit Span and Spatial Span; visuospatial memory through Rey-Osterrieth complex figure test; verbal learning and memory through California verbal learning test; and fine motor activity through grooved pegboard test. Sleep symptoms in narcolepsy patients were assessed with Epworth sleepiness scale, Ullanlinna narcolepsy scale, multiple sleep latency test, and nocturnal polysomnography. Relationship between cognitive functions and sleep symptoms in narcolepsy patients was also explored. Results: Compared with normal controls, narcolepsy patients showed poor performance in paced auditory serial addition (2.0 s and 2.4 s), digit symbol tests, and spatial span (forward)(t=3.86, p<0.01; t=-2.47, p=0.02; t=-3.95, p<0.01; t=-2.22, p=0.03, respectively). There were no significant between-group differences in other neuropsychological tests. In addition, results of neuropsychological test in narcolepsy patients were not correlated with Epworth sleepiness scale score, Ullanlinna narcolepsy scale score and sleep variables in multiple sleep latency test or nocturnal polysomnography. Conclusion: The current findings suggest that young narcolepsy patients have impaired attention. In addition, impairment of attention in narcolepsy might not be solely due to sleep symptoms such as excessive daytime sleepiness.