• 제목/요약/키워드: Dielectric mirror

검색결과 24건 처리시간 0.033초

유전체 다층 거울이 유기발광다이오드의 광효율 향상에 미치는 영향에 관한 광학 시뮬레이션 연구 (Effects of a Dielectric Multilayer Mirror on the Lighting Efficiency of Organic Light-Emitting Diodes Studied by Optical Simulation)

  • 이성준;고재현
    • 한국광학회지
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    • 제26권3호
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    • pp.139-146
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    • 2015
  • 본 논문에서는 유전체 다층 거울을 이용해 구성된 파브리-페롯 미소공진 구조가 유기발광다이오드(OLED)의 광효율에 미치는 영향을 유한차분 시간영역법과 광선추적법을 결합해 분석하였다. SiN과 $SiO_2$ 층을 교대로 쌓아 구성한 유전체 다층박막의 적용은 미소공진 효과를 강화시켜 OLED의 발광 스펙트럼의 협소화를 유도하였고 광추출효율도 수 % 증가하였다. 유전체 다층박막의 두께를 최적화함으로써 특정 파장에 대해 미소공진 효과를 일으킬 수 있었고 이는 OLED 발광색의 순도를 증가시키는데 활용될 수 있다. 광추출효율을 극대화하는 전자수송층의 최적 두께는 발광파장에 따라 달라졌는데, 이는 유기층 물질이 보이는 굴절률의 분산 때문인 것으로 생각된다.

A Magneto-optical Trap Below a Dielectric Coated Mirror Surface

  • Yu, Hoon;Lee, Lim;Lee, Kyung-Hyun;Kim, Jung-Bog
    • Journal of the Optical Society of Korea
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    • 제13권2호
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    • pp.223-226
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    • 2009
  • A Magneto-Optical Trap (MOT) for $^{87}Rb$ atoms near the surface of a dielectric coated mirror at the top of a small $20{\times}25{\times}40\;mm^3$ cell has been observed. Two beams of $3.3\;mW/cm^2$ were used for optical cooling and an anti-Helmholtz magnetic field with a spatial gradient of 9.1 G/cm was used for magnetic trapping. The thickness of the mirror coated on a cover glass was less than $100{\mu}m$. The mirror covered the top of a cell and the atom-chip was located outside the vacuum in order to exploit the long life time of the mirror and easy operation of the chip. The trapping position was found 5 mm beneath the mirror surface. The number of trapped atoms was roughly $3{\times}10^7$ atoms and the temperature was approximately a few tens mK. In this paper, we describe the construction of the mirror-MOT in detail.

1.55${\mu}{\textrm}{m}$에서 최적화된 유전체 다층막의 미러 특성 (The Mirror Characteristics of Dielectric Multilayer Optimized at 1.55${\mu}{\textrm}{m}$ Wavelength)

  • 박태성;정홍배;김명진;윤대원
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 추계학술대회 논문집
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    • pp.183-186
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    • 1995
  • The fabrication of dielectric multilayer mirror(DMM) optimized at the wavelength of 1.55$\mu\textrm{m}$ and its spectral properties were investigated. The materials used in the fabrication of DMM are TiO$_2$-SiO$_2$, which have the advantage of yielding high reflectance for relatively small numbers of layers. The optical constants of TiO$_2$single film were obtained by using a modified envelope method. The reflectances of DMMs with 3,7,11 and 23 layers were 58%, 89%, 97% and 99.9% at the wavelength of 1.55$\mu\textrm{m}$, respectively.

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ZERODUR의 저손실거울의 산란에 대한 연구 (A study on scattering in low loss mirror with superpolished ZERODUR)

  • 이범식;유연석;이재철
    • 한국광학회:학술대회논문집
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    • 한국광학회 2007년도 하계학술발표회 논문집
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    • pp.187-188
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    • 2007
  • Four kinds of mirror substrates with same surface roughness were fabricated. On those substrates, a dielectric multi-layer coating with high reflectivity was deposited by ion beam sputtering technique. Most of the fused silica mirrors showed lower scattering than the ZERODUR mirrors one, which deposited on substrates similar in surface roughness. The ZERODUR mirrors scattering strongly depend on the micro-structure of $Ta_2O_5/SiO_2$ thin films wear deposited on ZERODUR substrates.

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CMOS 일체형 미세 기계전자시스템을 위한 집적화 공정 개발 (Chip-scale Integration Technique for a Microelectromechnical System on a CMOS Circuit)

  • 이호철
    • 한국정밀공학회지
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    • 제20권5호
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    • pp.218-224
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    • 2003
  • This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

Design of Concentrating System for Solar Side-pumped Slab Laser

  • Fan, Wentong;Liu, Yan;Guo, Pan;Deng, Rui;Li, Nan;Ding, Fukang;Li, Yasha;Zhou, Jun;Xie, Shiwei
    • Current Optics and Photonics
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    • 제4권1호
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    • pp.50-56
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    • 2020
  • The design of a concentration system for a solar side-pumped slab laser was investigated. The side size of the slab laser medium is 2 mm × 20 mm. Based on the principle of the edge ray, a secondary concentrating system consisting of a rectangular parabolic mirror (RPM) and a rectangular dielectric-filled compound parabolic concentrator (RDCPC) was demonstrated. The focal length of RPM is 1200 mm and the size is 734 mm × 2000 mm. The outlet size of the RDCPC is 2 mm × 20 mm. The concentration effect was analyzed by using Tracepro optical software. The results showed that the concentration efficiency reached 81.3% and the uniformity of the spot was 91.4% after optimization. This design of concentration system is of great reference value for a solar side-pumped slab laser.

SBC 시스템 구성을 위한 단순한 구조를 가지는 고효율 무편광 유전체 다층박막 회절격자 설계 (Design of a Simply Structured High-efficiency Polarization-independent Multilayer Dielectric Grating for Spectral Beam Combining)

  • 조현주;김관하;김동환;이용수;김상인;조준용;김현태;곽영섭
    • 한국광학회지
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    • 제31권4호
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    • pp.169-175
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    • 2020
  • 격자의 구조가 간단하고 격자의 대조비가 낮은 SBC 시스템 구성을 위한 무편광 유전체 다층박막 회절격자를 설계하였다. SBC 방법으로 결합한 빔의 빔 품질을 높게 유지하기 위하여 회절격자의 파면 왜곡이 최소화되는 구조를 제안하였으며, 오염에 의한 흡수가 발생하지 않고 회절격자를 제작할 수 있는 구조로 회절격자를 최적화 설계하였다. 설계된 회절격자는 1055 nm 중심파장에서 Littrow 각도로 입사하는 경우 무편광 -1차 회절 효율이 99.36%이었으며, 96% 이상의 무편광 회절 효율을 나타내는 공정 여분이 확보되어 있음을 확인하였다.

Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-l00nm Technology

  • Navakanta Bhat;Thakur, Chandrabhan-Singh
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제3권3호
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    • pp.139-144
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    • 2003
  • We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

TIS 방법을 이용한 유전체 고반사 거울의 산란 측정 (Scattering measurement of dielectric high reflection mirrors by TIS method)

  • 조현주;박흥진;황보창권;문환구;김진태;손승현;이재철
    • 한국광학회지
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    • 제8권4호
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    • pp.283-290
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    • 1997
  • 진공 증착법으로 수정 기판 위에 증착된 유전체 고반사 다층 박막의 산란을 TIS 방법을 이용하여 측정하였다. 기판온도 250~300.deg. C에서 증착한(Ta$_{2}$O$_{5}$/SiO$_{2}$) 다층 박막의 산란율은 0.048~0.050%이며 300.deg. C에서 4시간 열처리에 의하여 영향을 받지 않았다. 기판온도 250.deg. C에서 증착한 (TiO$_{2}$/SiO$_{2}$) 다층 박막의 산란율은 0.029%이며 열처리에 의하여 심한 인장 응력을 받았다. 두 다층 박막의 표면 거칠기는 거의 차이가 없었고 Ta$_{2}$O$_{5}$ 박막의 기둥이 TiO$_{2}$ 박막보다 작고 조밀도는 (Ta$_{2}$O$_{5}$/SiO$_{2}$) 다층 박막이 큰 것을 알 수 있었다. (Ta$_{2}$O$_{5}$/SiO$_{2}$) 다층 박막의 산란율이 큰 것은 Ta$_{2}$O$_{5}$ 박막이 더 조밀하고 기둥 크기가 작으므로 박막 내에 기둥 수가 증가하여 체적 산란이 증가하였기 때문인 것으로 판단된다. 것으로 판단된다.

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