• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.396-405
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• 2006

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

• Korean Journal of Computational Design and Engineering
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• v.17 no.4
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• pp.274-281
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• 2012

This paper proposed a control simulation method for design and verification of the transport system in an automobile assembly line based on digital manufacturing system. The design of the transport system involves two major activities: mechanical design (device specification) and electrical design (device behavior and system control). Conventionally, the simulation and emulation system of the transport system focuses on the abstract level, which mainly deals with design verification, alternative comparison, and system diagnosis. Although it can provide overall system visibility in monitoring how well it works in the process and view, its simulation models are not sufficiently realistic to be used for a detailed design or for implementation purposes. In this paper, a digital simulation model for a transport system in an automotive assembly line is constructed by adapting a digital manufacturing methodology. We use the concept of the "Virtual Probe", which transport a carrier instead of the belt of the conveyor. In conclusion, the proposed method is valuable in the process of test run in the shop floor. This method would reduce the time and effort for validating the manufacturing system and improve the productivity and integrity of the control program.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.2
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• pp.709-722
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• 2014

In the $21^{st}$ century, IT reform has led to the development of cyber-infrastructure owing to the outstanding enhancement of computer and network performance. The ripple effect has continued to increase. Accordingly, this study suggests a new computational research environment using mobile devices. In order to simplify the access of supercomputer, Science AppStore, task management and virtualization technologies are developed on mobile devices. User can be able to research by utilizing computational science SW such as compressible flow solver and nano device simulation tool that in installed on supercomputer in mobile environments. Also, this research environment makes it possible to monitor the simulation result and covers 14 university, 33 subjects, and 1,202 individuals.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.370-376
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• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.4
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• pp.784-799
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• 2013

This paper presents an adaptive rate control scheme for streaming-based content sharing service. This scheme delivers multimedia contents from a user device to another device or seamlessly redirects streaming service across heterogeneous user devices. In the proposed scheme, a streaming server adjusts video quality level according to the network and client status. Our scheme is different from other rate control schemes, because the video quality at the server is decided not only based on the available bandwidth, but also based on the device characteristics and bandwidth requirement at the access network. We also propose a bandwidth estimation method to achieve more equitable bandwidth allocations among streaming flows competing for the same narrow link with different Round Trip Times (RTTs). Through the simulation, we prove that our scheme improves the network stability and the quality of streaming service by appropriately adjusting the quality of the video stream. The simulation results also demonstrate the ability of the proposed scheme in ensuring RTT-fairness while remaining throughput efficient.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.294-297
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• 2018

This paper analyzes the losses of the switching device for a full bridge inverter connected to the grid. As the development of power conversion system, losses are dominant factors in judging the efficiency of a system. The losses of a switching device can be divided into switching loss and conduction loss, both of which can be estimated by analyzing periodic switching waveform. The switching loss is generated when the switch is turned on and off, while the conduction loss is generated when the switch is turned on. The estimated losses of the MOSFET switch are compared with the simulation results.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.101-102
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• 2017

This paper presents analysis of losses of switching device for full bridge inverter connected to grid. The losses are a dominant factor that judges efficiency of the system. The losses of switching device are divided to switching loss and conduction loss. They are can be estimated by analyzing periodic switching waveforms. The switching loss is generated at the point that turn-on and off. And the conduction loss is generated while the switch is on condition. The estimated losses of switch are compared to simulation result in this paper.

• Journal of computational fluids engineering
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• v.15 no.4
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• pp.53-59
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• 2010

Preliminary design of a ground plate, a device installed close to the aircraft model for wind tunnel test to simulate the ground effect, was performed by a numerical simulation. A two-dimensional numerical study was performed initially to decide the optimal leading edge and flap configurations. Then, three-dimensional studies were conducted to decide the optimal flap deflection angle for pressure distribution reduction since the plate and the plate supporting system generate static pressure difference between the upper and lower flow regions. Three-dimensional simulation additionally studied the effect of the clearance between the plate and the wind tunnel side wall. For the efficiency of computation, half model was simulated and a symmetric boundary condition was applied on the center plane. Based on the preliminary design, a ground plate was designed, manufactured and tested at the Korea Aerospace Research Institute(KARI) wind tunnel. The measured pressure differences versus flap deflection angle agreed well with the predicted results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.379-383
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• 2003

The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.12-17
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• 2004

The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of $1{\times}10^{-7}\;{\Omega}\;cm^2$, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.