• Transactions on Electrical and Electronic Materials
• /
• v.12 no.6
• /
• pp.245-248
• /
• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• Journal of information and communication convergence engineering
• /
• v.18 no.4
• /
• pp.222-229
• /
• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of Information Processing Systems
• /
• v.13 no.2
• /
• pp.268-284
• /
• 2017

The dorsal hand vein biometric system developed has a main objective and specific targets; to get an electronic signature using a secure signature device. In this paper, we present our signature device with its different aims; respectively: The extraction of the dorsal veins from the images that were acquired through an infrared device. For each identification, we need the representation of the veins in the form of shape descriptors, which are invariant to translation, rotation and scaling; this extracted descriptor vector is the input of the matching step. The optimization decision system settings match the choice of threshold that allows accepting/rejecting a person, and selection of the most relevant descriptors, to minimize both FAR and FRR errors. The final decision for identification based descriptors selected by the PSO hybrid binary give a FAR =0% and FRR=0% as results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.1
• /
• pp.18-26
• /
• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.35 no.1
• /
• pp.50-57
• /
• 2022

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

• Electrical & Electronic Materials
• /
• v.8 no.6
• /
• pp.727-736
• /
• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.6
• /
• pp.1260-1265
• /
• 2012

This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.2
• /
• pp.1-6
• /
• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.622-634
• /
• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.3
• /
• pp.1-6
• /
• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.