• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1431-1433
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• 1995

This paper describes the characteristics of Si Hall sensors fabricated on a SOI(Si-on-insulator} structure, in which the SOI structure was forrmed by SDB(Si-wafer direct bonding) technology. The Hall voltage and the sensitivity of implemented Si Hall devices show good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average $600V/A{\cdot}T$. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the product Sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. From these results, Si Hall sensors using the SOI structure presented here are very suitable for high-temperature operation.

• Journal of the Speleological Society of Korea
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• no.77
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• pp.21-30
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• 2007

Photo-lithography lies in the middle of the wafer fabrication process. It is often considered as the most critical step in the IC process. We use a mask in exposure steps of the photo-lithography. Typically, 20 to 25 different levels of masks are required to complete an IC device. That means, if a photo process can be developed with the use of only one photo mask, we can reduce more process cost. To satisfy this, we plan to develop an alternative photo mask. For this reason, we chose to use a LCD. We expect to develop a LCD panel that can be changed by electrical control. This is the main idea about the adjustive photo mask. The Photo mask made of LCD panel will replace the former one.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.195-201
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• 2000

Current Status: Good Electrical performance for high speed device, Solder joint reliability-Passed 1600 cycles for 4M SRAM(3.27mm DNP),-Passed 400 cycles for large die(5.71 mm DNP), Future Plan: Improving Board Level Reliability for large die size, Lead free solder evaluation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.162-165
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• 1991

Oxygen behaviors in CZ-silicon wafer, grown by the Lucky Advanced Materials Inc. that is a pioneer of silicon material industries in Korea, were investigated to simulate effects on the device performance of oxygen, neglecting the effect of other impurity content, defects and thermal history. Silicon wafers were annealed through simulated 16K SRAM thermal cycle. As initial oxygen concentration increased up to 16.7ppma the amount of oxygen precipitation increased up to 10.6ppma and the bulk microdefect density increased up to $10.3{\times}10^3/mm^2$, but the depth of the denuded zone decreased to $5.0{\mu}m$

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1686-1687
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• 2011

A microfabricated chip with in-channel electrochemical cell using interdigitated gold electrode was fabricated for sensitive electrochemical analysis. The gold electrodes were fabricated on glass wafer using thermal evaporator and were covered using PDMS mold containing microchannel for analyte and electrolyte. The active area of each electrode was $250\;{\mu}m{\times}200\;{\mu}m$ with a gap of 200 ${\mu}m$ between the electrodes. Microelectrodes results in maximum amplification of signal, since the signal enhancement effect due to cycling of the reduced and oxidized species strongly depends on the inter electrode distance. Analytes such as methylene blue and guanosine were characterized using the fabricated electrodes and their electrochemical characteristics were compared with conventional bulk electrodes. The device so developed shall find use as disposable electrochemical cell for rapid and sensitive analysis of electroactive species.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1998.04a
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• pp.302-307
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• 1998

In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a sub-micrometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. The vibration criteria of high sensitive equipment should be represented in the form of exactness and accuracy, because this is used as basic data for the design of building structure and structural dynamics of equipment. The study on the evaluation of the factors affecting the permissible vibration criteria is required to design the efficient isolation system of the semiconductor manufacturing of equipment. This paper deals with the properties of the effected factor for vibration criteria of high sensitive equipment.