• Journal of International Society for Simulation Surgery
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• v.3 no.2
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• pp.87-89
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• 2016

Le fort 1 osteotomy surgery is one of the most popular surgical methods for the treatment of patients with facial bone deformities. An intermediate wafer splint is used to fix the bone segment to the planned position, but there are many steps that can cause errors. To reduce these errors, we propose a method of using a surgical guide made with virtual surgical simulation.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.413-415
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• 1996

This paper presents a technique for fabricating an electro-optical microlens for microcolumn e-beam system. The device, named Self-Aligned Microlens (SAM) was realized by mixing surface and bulk micromachining technology. The microbridges were formed on both sides of silicon wafer symmetrically. The alignment error between the electrodes could be controlled within a few micrometers with also reducing the numbers of anodic bonding.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.329-329
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• 2016

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.105-108
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• 2020

In this study, experiments and simulations were conducted for a 1,200-V-class trench Si insulated-gate bipolar transistor (IGBT) with a small cell pitch below 2.5 ㎛. Presently, as a power device, the 1,200-V-class trench Si IGBT is used for automotives including electric vehicles, hybrid electric vehicles, and industrial motors. We obtained a breakdown voltage of 1,440 V, threshold of 6 V, and state voltage drop of 1.75 V. This device is superior to conventional IGBTs featuring a planar gate. To derive its electrical characteristics, we extracted design and process parameters. The cell pitch was 0.95 ㎛ and total wafer thickness was 140 ㎛ with a resistivity of 60 Ω·cm. We will apply these results to achieve fine-pitch gate power devices suitable for electrical automotive industries.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.296-299
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• 2008

The effects of radio frequency (RF) source power for decoupled plasma nitridation (DPN) process on the electrical properties and Fowler-Nordheim (FN) stress immunity of the oxynitride gate dielectrics for deep nano-technology devices has been investigated. With increase of RF source power, the threshold voltage (Vth) of a NMOS transistor(TR) decreased and that of a PMOS transistor increased, indicating that the increase of nitrogen incorporation in the oxynitride layer due to higher RF source power induced more positive fixed charges. The improved off-current characteristics and wafer uniformity of PMOS Vth were observed with higher RF source power. FN stress immunity, however, has been degenerated with increasing RF source power, which was attributed to the increased trap sites in the oxynitride layer. With the experimental results, we could optimize the DPN process minimizing the power consumption of a device and satisfying the gate oxide reliability.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.4
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• pp.1-9
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• 2012

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined, and numerical experiments are conducted.

• Journal of Integrative Natural Science
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• v.3 no.4
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• pp.237-240
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• 2010

Recently, number of studies for porous silicon have been investigated by many researchers. Multistructured porous silicon (PSi), distributed Bragg reflector (DBR) PSi, has been a topic of interest, because of its unique optical properties. DBR PSi were prepared by an electrochemical etch of $P^{{+}{+}}$-type silicon wafer of resistivity between 0.1 $m{\Omega}cm$ with square wave current density, resulting two different refractive indices. In this work, We have fabricated a simple and portable organic vapor-sensing device based on DBR porous silicon and investigated the optical characteristics of DBR porous silicon. DBR porous silicon have been characterized by FT-IR, Ocean optics 2000 spectrometer. The device used DBR PSi chip has been demonstrated as an excellent gas sensor, showing a great senstivity to a toxic vapor (TEP, DMMP, DEEP) at room temperature.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.4
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• pp.490-495
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• 1995

A bipolar junction transistor which exihibits 1000V breakdown voltage is designed and fabricated using FLR (Field Limiting Rings). Three dimensional effects on the breakdown voltage is investigated in the cylindrical coordinate and the simulation results are compared with the results in the rectangular coordinate. Breakdown voltage of the device with 3 FLR is simulated to be 1420V in the cylindrical coordinate while it is 1580V in rectangular coordinate. Bipolar junction transistor has been fabricated using the epitaxial wafer of which resistivity is 86 .OMEGA.cm and thickness is 105 .mu.m. Si$_{3}$N$_{4}$ and glass are employed for the passivation. Breakdown of the fabricated device is measured to be 1442V which shows better greement with the simulation results in cylindrical coordination.