• Journal of Magnetics
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• 제1권1호
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• pp.9-13
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• 1996

The effects of surface relaxation on surface and interface magnetism in Fe/Cr (001) are investigated using the highly precise all-electron total-energy full-potential linearized augmented plane wave method. The Fe-Cr interlayer spacing is deter-mined by total-energy calculation and it is found to be relaxed downward by 18%. For the relaxed system, the magnetic moment of surface Fe is highly suppressed to be $1.72\mu_B$compared to the unrelaxed case ($2.39\mu_B$). This reduction of magnetic moment is considered as a result of the enhanced hybridization between Fe-d and Cr-d states, which can be seen from the calculated density of states. This work suggests the importance of effect of relaxation to the surface and interface magnetism in Fe/Cr system.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.904-907
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• 2007

We reported a simplified circuit model to investigate the interface states and the quality of a-Si film based on a MIS structure using admittance spectroscopy. The model can be employed easily to monitor the fabrication process of thin-film transistor and to obtain the important parameters.

• Journal of Magnetics
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• 제10권1호
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• pp.1-4
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• 2005

We investigated the electronic structures and the magnetic properties of Ti-based intermetallic system of CoTi/FeTi/CoTi(110) surface and interface by using the all-electron full potential linearized augmented plane wave (FLAPW) method within the generalized gradient approximation (GGA). The calculated magnetic moments of interface Co and Fe atoms are 0.65 and 0.15 μ/sub B/, respectively. Surface and interface magnetism of CoTi/FeTi/CoTi(110) are discussed using the calculated density of states (DOS) and the spin densities.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권12호
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• 센서학회지
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• 제5권6호
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• pp.60-67
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• 1996

저온 remote PECVD $SiO_{2}$막을 이용하여 제조된 InSb MIS구조에서의 계면의 전기적 특성에 대하여 연구하였다. $105^{\circ}C$에서 증착시킨 $SiO_{2}$막을 이용한 MIS구조의 중간 에너지 대역폭에서의 계면상태밀도가 $1{\sim}2{\times}10^{11}\;cm^{-2}eV^{-1}$으로 평가되었다. 그러나, $105^{\circ}C$이상의 고온에서 제조된 MIS소자의 계면에는 다량의 계면준위 및 트랩 준위가 존재하였다. G-V측정으로부터 계산된 계면준위들의 시상수는 $10^{-4}{\sim}10^{-5}\;sec$였으며, 증착온도가 증가할수록 트랩밀도가 증가하여 C-V특성곡선의 이력특성이 증대되었다.

• 한국자기학회지
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• 제17권4호
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• pp.147-151
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• 2007

호이슬러 구조를 가진 반쪽금속 $Co_2$ZrSi와 반도체인 ZnTe이 (001)면을 따라 계면을 이루었을 때 전자구조, 자성 및 반쪽금속성을 총 퍼텐셜 선형보강평면파동(FLAPW) 방법을 이용하여 이론적으로 연구하였다. 모두 4가지 가능한 계면, 즉 ZrSi/Zn, ZrSi/Te, Co/Zn와 Co/Te을 고려하였다. 계산된 상태밀도로부터 4가지 계면에서 모두 반쪽금속성이 깨어졌음을 알 수 있었으나 Co/Te의 경우 페르미에너지에서 소수 스핀 상태밀도의 값은 영에 가까웠다. 계면에서 반쪽금속성이 파괴되는 것은 계면에서 원자들의 좌표수와 대칭성이 덩치상태와 달라지고 계면전자들 사이의 띠 혼성에 의해 덩치 $Co_2$ZrSi의 소수 스핀 띠간격에 계면상태들이 나타났기 때문이다. Co/Te의 계면에서 Co원자의 자기모멘트의 값은 "bridge"와 "antibridge" 위치에서 각각 0.68과 $0.78{\mu}_B$로서 이는 덩치 Co경우의 값($1.15{\mu}_B$)에 비하여 크게 감소한 것이다. Co/Zn에서 "bridge"와 "antibridge" 위치에 있는 Co원자의 자기모멘트는 각각 1.16과 $0.93{\mu}_B$의 값을 가졌다. 반면 ZrSi/Zn와 ZrSi/Te의 경우 계면 바로 밑층의 Co원자들은 $1.13{\sim}1.30\;{\mu}_B$ 사이의 자기모멘트를 가졌는데 이는 덩치 $Co_2$ZrSi에서의 값과 비슷하거나 약간 증가한 값이다.

• 한국전기전자재료학회논문지
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• 제15권8호
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• pp.664-670
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• 2002

The electrical characteristics of $ZnO-Pr_6O_{11}-CoO-Cr_2O_3-Y_2O_3$(ZPCCY)-based varistors were investigated with $Y_2O_3$ content in the range of 0.0~4.0 mol%. As $Y_2O_3$ content is increased, the average grain size was markedly decreased in the range of 18.6~3.2 $\mu m$ and the density of the ceramic was decreased in the range of 5.53 ~3.74 $g/\textrm{cm}^3$. While, the varistor voltage was increased in the range of 39.4~748.1 V/mm and the nonlinear exponent was in the range of 4.5~51.2 with increasing $Y_2O_3$ content. The addition of $Y_2O_3$ greatly enhanced the nonlinear properties of varistors, compared with the varistor without $Y_2O_3$. In particular, the varistors with $Y_2O_3$content of 0.5 mol% exhibited the highest nonlinearity, in which the nonlinear exponent is 51.2 and the leakage current is 1.3 $\mu A$. The donor concentration and the density of interface states were decreased in the range of (4.19~0.14) $\times$10$^{18}$ /㎤ and (5.38~1.15)${\times}10^{18}/\textrm{cm}^3$, respectively, with increasing $Y_2O_3$ content.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.65-65
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• 2009

High temperature silicon carbide Schottky diode was fabricated with Au deposited on poly 3C-SiC thin film grown on p-type Si(100) using atmospheric pressure chemical vapor deposition. The charge transport mechanism of the diode was studied in the temperature range of 300 K to 550 K. The forward and reverse bias currents of the diode increase strongly with temperature and diode shows a non-ideal behavior due to the series resistance and the interface states associated with 3C-SiC. The charge transport mechanism is a temperature activated process, in which, the electrons passes over of the low barriers and in turn, diode has a large ideality factor. The charge transport mechanism of the diode was analyzed by a Gaussian distribution of the Schottky barrier heights due to the Schottky barrier inhomogeneities at the metal-semiconductor interface and the mean barrier height and zero-bias standard deviation values for the diode was found to be 1.82 eV and $s_0$=0.233 V, respectively. The interface state density of the diode was determined using conductance-frequency and it was of order of $9.18{\times}10^{10}eV^{-1}cm^{-2}$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.47-50
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• 2000

This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.