• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1948-1951
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• 2002

In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.12
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• pp.65-73
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• 2014

In this paper, the detection scheme of the voltage variation using a two difference voltage is proposed. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on a d-q transformation using an all-pass filter (APF). The APF generates a virtual q-axis voltage component with $90^{\circ}$ phase delay but the APF cannot generate the virtual q-axis voltage depending on the phase of the grid voltage. To overcome the problem, q-axis voltage component is generated from difference between the current and previous value of d-axis voltage component in the stationary reference frame. However, the difference voltage around the zero crossing is not enough to detect the voltage sag. Therefore, the new detection scheme using the two difference voltage which can detect the sag around the zero crossing voltage is proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• Journal of IKEEE
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• v.15 no.1
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1190-1196
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• 2014

This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).