• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.105-112
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• 1999

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL(Delay Lock Loop), Tau-dither Loop, SO(Synchronous Osillator) etc., in the sychronous method. But since there are analog operations, the setting is difficult and circuit size is large. In this paper we proposed Digital Delay Lock Loop (DDLL) and estimated it's performance through the experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.79-82
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• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.223-228
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• 2006

The main purpose of this paper is to describe the code tracking performance of a non-coherent digital delay lock loop (DLL) or coherent DLL while tracking GNSS signal in the presence of signal masking. The masking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal masking is used to remove random or periodic interference. Three types of the masked signal are considered - no masking, periodic masking, and random masking of the signal input to the receiver. The mean time to lose lock (MTLL) of the code tracking loop are evaluated, and some numerical result and simulation results are reported. Finally, the steadystate tracking errors on the performance of the tracking loop in interference environment are also presented.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.16-24
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• 1981

The delay-lock loop (DLL) is a statistically optimum device for tracking the de]ay difference between two correlated waveforms. In this paper an extended n - $\Delta$ (n=1,2,3‥‥) DLL is described, and its baseband performance including the frequency to lose lock is analyzed. The present DLL system employs a correlator and a pseudonoise sequence synthesizer that has been improved from the previously used ones The shape of the correlator characterigtic has the form of expanded S-curve. Despite of increase noise, this extended DLL has desirable characteristics in tracking range and initial synchronization time. Comparing a 3 - $\Delta$ DLL with a 1 - A DLL, the former Bives three times faster initial synchronization time with the serial synchronization method, and gives two times immunity against doppler shift.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.