A Fast lock-on time Delay Locked Loop with selective starting point

빠른 lock-on time을 위한 선택적 시작점을 갖는 DLL

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.