• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.33-40
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• 1992

Several etching phenomena were observed and analyzed in diaphragm process performed on 4-inch (100) Si wafers for sensor application. In case of deep etching to above 300$\mu$m depth, the etch-defects appeared at etched surface could be classified into three categories such as hillocks, reaction products, and white residues. It was known that the hillock had a pyramidal shape or trapizoidal hexahedron structure depending on the density and size of the reaction products. The IR spectra showed that the white residue, which was due to the local over-saturation of Si dissolved in solution, was mostly Si-N-O compounds mixed with a small amount of H and C etc. Also, the difference in both the existence of etch-defects and etch rate distribution over a whole wafer was investigated when the etched surfaces were downward, upward horizontally and erective in etching solutions. The obtained data were analyzed through flow pattern in the etching bath. As the results, the downward and erective postures were favorable in the etch rate uniformity and the etch-defect removal, respectively.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1963-1967
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• 1996

This paper describes the analysis, design, and silicon-fabrication of a fluidic proportional amplifier, which is the most important element of fluidic logic circuits. First, FEM(finite element method) analyses were performed, using the Fluent computational fluid dynamics program, and design geometries were optimized. Then, a $40\;{\mu}m$-deep amplifier was fabricated in silicon using anisotropic dry etching.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.59-62
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• 2005

백색 LED 램프를 제조하는 공정에서 램프간의 전기적 개방상태의 절연상태를 유지하기 위해 사파이어 기판 위에 성장된 GaN 계 반도체 에피박막층을 제거하기 위해 유도 결합형 플라즈마 식각 공정을 이용하였다. 4 미크론의 두께를 갖는 GaN 층을 식각하는데 있어 식각 방지 마스킹 물질로 포토레지스트, $SiO_2,\;Si_{3}N_4$ 및 $Al_{2}O_3$를 시험하였다. 동일한 전력 및 가스유량상태에서 $Al_{2}O_3$만 에피층을 보호할 수 있음을 확인하였다.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.4
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• pp.149-154
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• 2004

This paper presents a silicon probe tip for vertical probe card application. The silicon probe tip was fabricated using MEMS technology such as porous silicon micromachining and deep- RIE (reactive ion etching). The thickness of the silicon epitaxial layers was 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$, respectively. The width and length were 40 ${\mu}{\textrm}{m}$ and 600 ${\mu}{\textrm}{m}$, respectively. The probe structure was a multilayered structure and was composed of Au/Ni-Cr/Si$_3$N$_4$/n-epi layers. The height of the curled probe tip was measured as a function of the annealing temperature and time. Resistance characteristics of the probe tip were measured using a touchdown test.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.172-173
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• 2002

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.116-117
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• 2009

식각 공정변화 즉 상부 ICP 파워, 반응기 압력, 실리콘 기판 온도변화에 따른 실리콘 딥 비어 (deep via) 의 형상 변화 메커니즘을 연구하였다. 메커니즘을 연구하기 위해 $SF_6/O_2$ 플라즈마에 노출된 실리콘 기판의 공정변화에 따른 표면 온도변화를 실시간으로 측정하여 플라즈마 내 positive ions의 거동을 분석하였다. 실리콘 기판의 표면온도를 상승시키는 주된 요인은 positive ions임을 확인할 수 있었으며 이는 기판에 적용된 negative voltage로 인하여 나타난 이온포격이 그 원인임을 알 수 있었다. 상대적으로 radical은 실리콘 표면온도 상승에 큰 역할을 하지 못하였다. 기판 표면온도가 상승 할수록 실리콘 딥 비어 구조에 undercut, local bowing과 같은 측벽 식각이 활성화됨을 확인할 수 있었으며 이는 기판에 들어오는 positive ions가 측벽식각을 유도하는 것으로 해석할 수 있었다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.12-17
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• 2003

본 연구에서는 MICP Etching system 을 이용한 Via contact 및 Deep contact hole etch process 특성을 연구하였다. Langmuir probe 를 이용한 MICP source 의 Plasma density & electron temperature 측정하였고 탄소와 플로우르를 포함하는 혼합 Plasma 를 형성하여 RF frequency, wall temperature, chamber gap, gas chemistry 등의 변화에 따른 식각 특성을 조사하였다. Plasma density 는 1000w 에서 $10^{11}$/$cm^3$ 이상의 high density plasma와 uniform plasma 형성을 확인하였고 $CH_{2}F_{2}$와 CO의 적절한 혼합비를 이용하여 Oxide to PR 선택비가 10 이상인 고선택비 조건을 확보하였다. 고선택비 형성에 따라 Polymer 형성이 많이 되었고 이를 개선하기 위하여 반응 챔버의 온도 조절을 통하여 Polymer 증착 방지에 효과적인 것을 확인하였다. MICP source를 이용하여 탄소와 플로우르의 혼합 가스와 식각 챔버의 온도 조절에 의한 선택비 증가를 확보하여 High Aspect Ratio Contact Hole Etch 가능성을 확보하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.