• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.37-42
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• 2019

In this paper, we propose a syndrome decoding scheme that can correct two errors for single error correcting Hamming codes within a code length. The decoding scheme proposed in this paper has the advantage of significantly improving the error rate performance compared to the decoder complexity by correcting multiple errors without substantially increasing the decoding complexity. It is suitable for applications in which the energy use of encoder/decoder is extremely limited and the low error rate performance is required, such as IoT communications and molecular communications. In order to verify the improvement of the error rate performance of the Hamming code with the proposed decoding scheme, we performed simulation on Hamming codes with short code length in the AWGN and BPSK modulation environments. As a result, compared with the conventional decoding method, the proposed decoding scheme showed performance improvement of about 1.1 ~ 1.2[dB] regardless of the code length of the Hamming code.

• ETRI Journal
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• v.26 no.2
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• pp.101-111
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• 2004

This paper presents a near-optimum blind decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television. By adopting a modified trellis decoder (MTD) with a trace- back depth of 1 for the decision device in the DFE, we obtain a hardware-efficient, blind DFE approaching the performance of an optimum DFE which has no error propagation. In the MTD, the absolute distance is used rather than the squared Euclidean distance for the computation of the branch metrics. This results in a reduction of the computational complexity over the original trellis decoding scheme. Compared to the conventional slicer, the MTD shows an outstanding performance improvement in decision error probability and is comparable to the original trellis decoder using the Euclidean distance. Reducing error propagation by use of the MTD in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer, and the difference is prominent at the trellis decoder following the blind DFE.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.719-725
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• 1986

Reed-solomon(R-S) code is very effective to coerrect both random and burst errors over a noise communication channel. However, the required hardware is very complex if the B/M algorithm was employed. Moreover, when the error correction system consists of two R-S decoder and de-interleave, the I/O data bns lines becomes 9bits because of an erasure flag bit. Thus, it increases the complexity of hardware. This paper describes the R-S decoder which consisits of a error correction section that uses a direct decoding algorithm and erasure generation section and a erasure generation section which does not use the erasure flag bit. It can be shown that the proposed R-S dicoder is very effective in reducing the size of required hardware for error correction.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.30-33
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• 2023

The recent scholarly focus has been directed towards the expeditious and accurate detection of salient objects, a task that poses considerable challenges for resource-limited edge devices due to the high computational demands of existing models. To mitigate this issue, some contemporary research has favored inference speed at the expense of accuracy. In an effort to reconcile the intrinsic trade-off between accuracy and computational efficiency, we present novel model for salient object detection. Our model incorporate group-wise attentive module within the decoder of the encoder-decoder framework, with the aim of minimizing computational overhead while preserving detection accuracy. Additionally, the proposed architectural design employs attention mechanisms to generate boundary information and semantic features pertinent to the salient objects. Through various experimentation across five distinct datasets, we have empirically substantiated that our proposed models achieve performance metrics comparable to those of computationally intensive state-of-the-art models, yet with a marked reduction in computational complexity.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1123-1126
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• 1999

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.