• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.1
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• pp.87-96
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• 2002

This paper proposes an efficient decimation filter structure in programmable down converter for software radio. The decimation filter consists of the cascaded integrator-comb(CIC) filter, a compensation filter for CIC, cascaded comb and modified halfband filters, and programmable FIR filter. Since the compensation filter is used in CIC, the passband drooping is compensated and stopband attenuation is improved. Therefor the more decimation can be implemented in CIC filter. The compensation filter in CIC reduced the computational complexity of other decimation filters and the coefficients of PFIR, thereby achieving a significant hardware reduction over existing approaches. We can reduce the multiply operator by 20% in hardware and operation by 50% as compared with PDC of Harris.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.13-20
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• 2001

Adaptive digital filters with long impulse response such as acoustic echo canceller and active noise controller suffer from slow convergence and computational burden. Subband techniques and multirate signal processing have been recently developed to improve the problem of computational complexity and slow convergence in conventional adaptive filter. Any FIR transfer function can be realized as a serial connection of interpolators followed by subfilters with a sparse impulse response. In this case, each interpolator which is related to the column vector of Hadamard matrix has band-pass magnitude response characteristics shifted uniformly. Subband technique using Hadamard transform and decimation of subband signal to reduce sampling rate are adapted to system modeling and acoustic noise cancellation In this paper, delayless subband structure with nonuniform bandwidth has been proposed to improve the performance of the convergence speed without aliasing due to decimation, where input signal is split into subband one using tree-structured filter bank, and the subband signal is decimated by a decimator to reduce the sampling rate in each channel, then subfilter with sparse impulse response is transformed to full band adaptive filter coefficient using Hadamard transform. It is shown by computer simulations that the proposed method can be adapted to general adaptive filtering.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.2-17
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• 1999

Interpolated second order polynomials(ISOP's) are proposed to design efficient cascaded integrator-comb(CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOP's can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOP's are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified half band filter(MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for a programmable downconverter is a cascade of a CIC filter, an ISOP, MHBF's and a programmable finite impulse response(FIR) filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.777-784
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• 2004

In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.630-638
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• 2001

This paper has been proposed a structure composed of FIRs and IIR filters as digital decimation filter to compensate the drooping inband on the high precision AU chips. The area of chip has been reduced compared with the conventional structure because the RAM and MAC is reduced. The passband ripple$(\leq\; 0.4535 \times fs)$, passband attenuation(at $\; 0.4535 \times fs$ and stopband attenuation$(\geq\; 0.59\times fs)$ of the 6th-order $\Delta\Sigma$ modulator and digital decimation filter had $\pm0.0007[dB]$, -0.0013[dB] and -110[dB] respectively. Also the inband group delay, which was almost same compared with the conventional digital decimation filter structure, was 30.07/fs[s] band the error of group delay was 0.1672%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.139-142
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• 2001

In this paper, a new CIC filter structure for reduction of passband droop in CIC decimation filter is proposed. For improvement of passband characteristics, the 1st order Generalized Comb Filter(UF) is proposed in addition to the conventional CIC decimation filter. By using this filter, it is shown that passband droop is remarkably reduced and aliasing attenuation is slightly increased. We also propose how to find the optimum filter coefficient Furthermora, it is shown that choices for GCF are possible in terms of the number of Half-Band filter. Passband droops and aliasing attenuations of the proposed structure are compared with those of the CIC structures using conventional sharpening techniques.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.826-835
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• 1988

In this paper, we analyze the generation of an image pyramid as a 2-dimensional decimation-interpolation process, and suggest a performance index of FIR filter for decimation and interpolation filter. Until now, most deciamtion and interpolation filters are designed via the approximation of the impulse response of an ideal filter. In this paper, however, we propose a new performance index that minimizes the maximum frequency-weighted mean square error between the desired and the generated interpolated signal, and propose an optimal half-band filter based on the proposed performance index as an example. Some simulation results with real images show that the proposed optimal half-band filter yields a higher PSNR as well as the more preferable image quality, in comparison with other currently used filters with the same computational complexity.