• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.722-737
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• 2011

In this paper, we propose an estimation of network jitter that occurs when transmitting TCP packets containing MPEG-2 TS in progressive streaming service over wired or wireless Internet networks. Based on the estimated network jitter size, we can calculate required de-jitter buffering time to absorb the network jitter at the receiver side. For this purpose, by exploiting the PCR timestamp existing in the TS packet header, we create a new timestamp information that is marked in the optional field of TCP packet header to estimate the network jitter. By using the proposed de-jitter buffering scheme, it is possible to employ the conventional T-STD buffer model without any modification in the progressive streaming service over IP networks. The proposed method can be applicable to the recently developed international standard, MPEG DASH (dynamic adaptive streaming over HTTP) technology.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.867-871
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• 2013

In this paper, a major factor in determining voice quality that corresponds to the jitter and jitter buffer algorithm for removing jitter will be described. We analyze various jitter buffer algorithms and suggest ways to improve performance of jitter buffer algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.125-132
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• 2015

PCI Express is high-speed point-to-point serial protocol, the system is designed by analysing loss and jitter through Eye Diagram. It is necessarily analyzing high speed serial signals when the PCI Express Gen3 which has 8Gbps physical signal speed is designed especially. This paper deals with topology extraction, channel analysis, extraction of s-parameters and system signal integrity simulation within transceiver buffer models through PCI Express Gen3 server connecting switch system design. Optimal parameters of transmitter buffer equalizer are found through solution space simulation of de-emphasis and preshoot parameters to compensate channel loss.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Phonetics and Speech Sciences
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• v.2 no.4
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• pp.75-82
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• 2010

Many previous studies based on respiratory characteristics of Idiopathic Parkinson's Diseases (IPD) patients have not controlled related factors appropriately. Accordingly, these studies produced discordant results. Furthermore, there is currently a lack of studies that can provide precise explanations on the characteristics of respiration and phonation. This study included a total of 40 subjects: 20 mixed gender de novo IPD patients ranging in age from 50 to 80 (Hoehn & Yahr stage 1~3), and 20 normal subjects with similar matches for age and gender. All participants were controlled based on their gender, age, height, weight, vocal fold function, cognitive abilities, and depression factors. K-MMSE (Korean-Mini Mental State Examination), nVHI-10 (new Voice Handicap Index), and KGDS (Korean Form of Geriatric Depression Scale) were evaluated to select this study subjects. In order to compare respiratory functions between the two groups, FVC, FEV1, and FEV1/FVC were measured using microQuark, a PC-based spirometer. CSL was used by measure MPT and PAS was used to measure MFR. To investigate the characteristics of phonation ability, CSL was used to measure jitter and shimmer, while PAS was used to measure Psub. In order to compare the respiratory function averages and phonation ability between the two groups, statistical analysis was conducted using SPSS (version 12.0). The results of this study showed that most de novo IPD patients were included in the normal average range of respiratory and phonatory ability. But the respiratory and phonatory ability of de novo IPD patients showed lower tendency as compared with the normal group. When the average of respiratory and phonatory ability among the gender was compared, the difference of males was greater than the difference of females.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.52-58
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). The recent TCON requires wide range frequency operation of $8\sim135MHz$ in PLL. In order to be satisfied this requirement the new V-I converter.circuit. The V-I converter of new architecture increased the minimum/maximum current ratio which widens the operation frequency range of VCO's md also guaranteed linearity of VCO's. The proposed PLL circuits in FPD TCON show the measuring performance of loops RMS jitter in the range of $8\sim135MHz$. The designed circuit was fabricated in 1-ploy 3-metal 0.25um TSMC process technology and has a operation range or $8\sim135MHz$ with 2.5V power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.