• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.163-167
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• 2003

In this paper, an air-suspension type RF MEMS inductor is fabricated, and an appropriate de-embedding scheme for 3-dimenstional MEMS structure is applied and verified with inductance calculation algorithm. With the presented de-embedding method, parasitics from contanct pads and feeding lines are effectively and accurately de-embedded using open and short calibration procedure, and only spiral and posts can be characterized as a high-Q inductor structure. The validity of the de-embedding method is verified by the comparison of the measured and calculated inductances of two 1.5 and 2.5 turn square spiral inductors. The open-short de-embedded inductance error is below 5% each case in comparison with the calculated value based on H.M. Greenhouse's algorithm.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.258-265
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• 2015

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.53-58
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• 2012

A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1668-1669
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• 2011

본 논문에서는 Pogo Pin의 신호 전달 특성을 Ansys사의 Full wave simulation tool(HFSS)를 사용하여 분석하였고, 측정을 위해서 필요한 interface(Guide PCB)의 특성은 2-port de-embedding 방법을 이용하여 제거하였다. Guide PCB의 특성이 제거된 Pogo Pin만의 시뮬레이션 결과와 circuit simulator인 Agilent사의 ADS를 사용하여 Guide PCB의 특성을 de-embedding한 결과를 비교 검증하였고, Pogo Pin의 시뮬레이션 결과와 PCB의 특성을 de-embedding한 결과가 0~8 GHz까지 일치하는 것을 확인하였다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.125-126
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• 2015

통신 시스템에서의 더 늘어난 대역폭(Band Width)의 수요로 인해 집적회로(Integrated Circuit)에서 더 높은 동작 주파수(Operating Frequency)를 필요로 하게 되었다. 고주파 영역에서는 SRF(Self Resonance Frequency) 문제와 소자 값의 정확성(Accuracy)에 대한 문제 때문에 정수소자(Lumped Element)를 이용하여 해석을 할 수 없으며 이로 인하여 어떠한 회로의 전기적 특성을 평가함에 있어서 전송선로(Transmission Line)를 이용하여 해석을 하는 것은 중요한 역할을 하게 되었다. 이러한 해석을 위해 순수한 내부 특성을 얻기 위하여 디 임베딩(De-Embedding)이라는 기법이 사용되고 있으나, 알려진 몇 가지의 방법들은 인터커넥터 부분을 완벽히 나타내지 못한다. 따라서 본 논문에서는 1-Port 측정을 기반으로 한 8-Term Error을 이용한 디 임베딩(De-Embedding) 방법을 이용하여 넓은 주파수 영역에서의 교정 값을 얻는 방법에 대하여 소개하고자 한다.

• ETRI Journal
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• v.32 no.6
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• pp.969-971
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• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.543-551
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• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.217-220
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• 2001

CaN(gallium nitride) MODFET(modulation doped field effect transistor) large signal model was studied using Modified Materka-Kacprzak large signal MODFET model. using the Dambrine's method［3, at 45MHz-40㎓, Measured S-parameter and DC characteristics. based on measuring results, small signal parameter extraction was conducted. by the cold FET［4］method, measured parasitic elements were de-embedding. Extracted small signal parameters were modeled using modified Materka model, a sort of fitting function reproduce measuring results. to confirm conducted large signal modeling, modeled GaN MODFET's DC, S-parameter and Power characteristics were compared to measured results, respectively. by results were represented comparatively agreement, this paper showed that modified Materka model was useful in the GaN MODFET large signal modeling.

• Journal of electromagnetic engineering and science
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• v.12 no.1
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• pp.122-127
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• 2012

Post-wall waveguide structures have attracted a great deal of attention for micro- and millimeter-wave applications. One of the waveguide’s applications is a slotted waveguide array. In order to design the slotted array, the characteristics of a slot unit alone on the post-wall waveguide should be investigated. In this paper, a method for extracting the S-parameters of a unit slot is proposed. This simple method requires only two kinds of waveguides: waveguides without a slot unit and waveguides with a slot unit. Three kinds of slot units are fabricated, and the extracted results show a high level of agreement with predicted (simulated) results. With this method, the equivalent slot length can also be found.