• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.3
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• pp.190-197
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• 2000

A graphic vehicle modeling pre-processing program and a visualization post-processing program have been developed for AutoDyn7, which is a special program for vehicle dynamics. The Rapid-App for GUI(Graphic User Interface) builder and the Open Inventor for 3D graphic library have been employed to develop these programs in Silicon Graphics workstation. A Graphic User Interface program integrates vehicle modeling pre-processor, AutoDyn7 analysis processor, and visualization post-processor. In vehicle modeling pre-processor, vehicle hard point data for a suspension model are automatically converted into multibody vehicle system data. An interactive graphics capabilities provides suspension modeling aides to verify user input data interactively. In visualization post-processor, vehicle virtual test simulation results are animated with virtual testing environments.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.71-80
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• 2004

This paper describes embedded processor architecture design which is applicable to multimedia in mobile platform The main description is based on basic processor architecture and consideration about energy efficiency when used in mobile platform To design processor data path architecture (pipeline, branch prediction, multiple issue superscalar, function unit number) which is optimal to multimedia application and cache hierarchy and its structure, we have nut the simulation with variant architecture using MPEG4 test bench as multimedia application. We analyzed energy efficiency of architecture to check if it is applicable to mobile platform and decide basic processor architecture based on analysis result. The suggested basic processor architecture not only can be applied to mobile platform but also can be applied to basic processor architecture of configurable processor which is designed through automatic design environment.

• ETRI Journal
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• v.31 no.6
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• pp.709-716
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• 2009

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single-instruction multiple-data (DP-SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P-SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD-based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P-SIMD, and DP-SIMD. Experimental results show that the DP-SIMD control method is more efficient than SIMD and P-SIMD control methods by about 15% and 14%, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.381-382
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• 2008

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.438-443
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• 2005

Handy paint rollers with simple or no patterns are generally used to transcribe its design to a wall just after painting. However, the types of the patterns are limited to several conventional ones, so that interior planners' or decorators' demands are gradually tending to getting attractive roller designs. In order to obtain abundant kinds of the roller designs, a new advanced 3D machining method should be established for cylindrical models. In this paper, a post-processor that can generate suitable NC data is proposed for multi-axis NC machine tools with a rotary unit. The 3D machining system with the post-processor is also presented for an attractive interior decorating. The machining system allows us to easily transcribe the relief designs from on a flat model to on a cylindrical model. The effectiveness of the proposed 3D machining system using the post-processor is demonstrated through some machining experiments.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.