• 전기화학회지
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• 제5권3호
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• pp.153-158
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• 2002

전해전착법을 이용한 상감(damascene)구리 배선 충전시 레벨러 효과에 대해 연구하였다. 레벨러를 첨가한 도금액과 첨가하지 않은 도금액을 제조하여 선 폭이 $0.37{\mu}m,\;0.18{\mu}m$인 선형 트렌치를 충전한 후 field emission scanning electron microscope(FE-SEM)로 트렌치 단면을 관찰하였다. 레벨러로 Janus Green B를 사용하였으며, 억제제로서 polyethylene glycol(PEG), 촉진제로서 3-mercapto-1-propansulfonic acid를 사용하였다 레벨러를 첨가하지 않은 경우 $0.37{\mu}m$(종횡비 2.7:1) 트렌치를 공극 없이 충전할 수 있었으나 $0.18{\mu}m$(종횡비 5.25:1) 트렌치에서는 공극(void)이 형성되었다. 레벨러를 첨가한 경우에는 $0.18{\mu}m$ 트렌치를 공극 없이 충전할 수 있었다. 레벨러를 첨가하지 않은 경우 트렌치 모서리에서의 전착속도를 충분하게 억제하지 못하고 거칠게 전착되어 미세한 트렌치 충전시 공극을 형성한 반면, 레벨러를 첨가한 경우는 트렌치 상부모서리에서의 전착속도를 억제하고 균일한 전착을 유도하여 미세한 트렌치를 공극 없이 채울 수 있었다.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.37-41
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• 2012

Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 $SiO_2$와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다.

• 대한기계학회논문집A
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• 제33권10호
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• pp.1023-1028
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• 2009

Cleaning is required following CMP (chemical mechanical planarization) to remove particles. The minimization of particle residue is required with each successive technology generation, and the cleaning of wafers becomes more complicated. In copper damascene process for interconnection structure, it utilizes 2-step CMP consists of Cu and barrier CMP. Such a 2-steps CMP process leaves a lot of abrasive particles on the wafer surface, cleaning is required to remove abrasive particles. In this study, the chemical mechanical cleaning(CMC) is performed various conditions as a cleaning process. The CMC process combined mechanical cleaning by friction between a wafer and a pad and chemical cleaning by CMC solution consists of tetramethyl ammonium hydroxide (TMAH) / benzotriazole (BTA). This paper studies the removal of abrasive on the Cu wafer and the cleaning efficiency of CMC process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• 전자공학회논문지D
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• 제36D권12호
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• pp.37-42
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• 1999

본 논문에서는 차세대 집적회로의 핵심공정으로 부각되고 있는 CMP를 이용한 Cu Damascene 공정을 연구하였다. E-beam lithography, $SiO_2$ CVD 및 RIE, Ti/Cu CVD등의 제반 단위 공정을 연구하였으며, 연구된 단위공정으로 2창의 Cu금속 배선을 제작하였다. CMP 단위공정 연구결과, hend 압력 4 PSI, table 및 head 속도 25rpm, 진동폭 10mm, 슬러리 공급량 40ml/min에서 연마율 4,635 ${\AA}$/min, Cu:$SiO_2$의 선택율 150:1, 평탄도 4.0%를 얻었다. E-beam 및 $SiO_2$ vialine 공정연구결과, 100 ${\mu}C/cm^2$ 도즈와 6분 30초의 현상 및 1분 10초의 에칭시간으로 약 0.18 ${\mu}m\;SiO_2$ via-line을 형성하였다. 연구된 단위공정으로 sub-0.2 ${\mu}$의 Cu 금속라인을 제작하였으며, Cu void 및 Cu의 peeling으로 인한 다층공정시의 문제점과 재현성 향상 방법에 대해 논의하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1880-1884
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• 2008

Cleaning is required following CMP (chemical mechanical planarization) to remove particles. The minimization of particle residue is required with each successive technology generation, and the cleaning of wafers becomes more complicated. In copper damascene process for interconnection structure, it utilizes 2-steop CMP consists of Cu CMP and barrier CMP. Such a 2-steps CMP process leaves a lot of abrasive particles on the wafer surface, cleaning is required to remove abrasive particles. In this study, the buffing is performed various conditions as a cleaning process. The buffing process combined mechanical cleaning by friction between a wafer and a buffing pad and chemical cleaning by buffing solution consists of tetramethyl ammonium hydroxide (TMAH)/benzotriazole(BTA).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.537-537
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• 2008

Copper (Cu) has been widely used for interconnection structure in intergrated circuits because of its properties such as a low resistance and high resistance to electromigration compared with aluminuim. Damascene processing for the interconnection structure utilizes 2-steps chemical mechanical polishing(CMP). After polishing, the removal of abrasive particles on the surfaces becomes as important as the polishing process. In the paper, buffing process for the removal of colloidal silica from polished Cu wafer was proposed and demonstrated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.101-102
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• 2006

PZT thin films, which are the representative ferroelectric materials in ferroelectric random access memory (FRAM), have some serious problem such as the imprint, retention and fatigue which ferroelectric properties are degraded by repetitive polarization. BL T thin film capacitors were fabricated by plasma etching, however, the plasma etching of BLT thin film was known to be very difficult. In our previous study, the ferroelectric materials such as PZT and BLT were patterned by chemical mechanical polishing (CMP) using damascene process to top electrode/ferroelectric material/bottom electrode. It is also possible to pattern the BLT thin film capacitors by CMP, however, the CMP damage was not considered in the experiments. The properties of BLT thin films were changed by the change of polishing pressure although the removal rate was directly proportional to the polishing pressure in CMP process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1384-1385
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• 2006

Platinum is a candidate of top and bottom electrode in ferroelectric random access memory and dynamic random access memory. High dielectric materials and ferroelectric materials were generally patterned by plasma etching, however, the low etch rate and low etching profile were repoted. We proposed the damascene process of high dielectric materials and ferroelectric materials for patterning process through the chemical mechanical polishing process. At this time, platinum as a top electrode was used for the stopper for the end-point detection as Igarashi model. Therefore, the control of removal rate in platinum chemical mechanical polishing process was required. In this study, an addition of $H_{2}O_{2}$ oxidizer to alumina slurry could control the removal rate of platinum. The removal rate of platinum rapidly increased with an addition of 10wt% $H_{2}O_{2}$ oxidizer from 24.81nm/min to 113.59nm/min. Within-wafer non-uniformity of platinum after chemical mechanical polishing process was 9.93% with an addition of 5wt% $H_{2}O_{2}$ oxidizer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.