Journal of the Korean Institute of Telematics and Electronics D (전자공학회논문지D)
- Volume 36D Issue 12
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- Pages.37-42
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- 1999
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- 1226-5845(pISSN)
Studies on Cu Dual-damascene Processes for Fabrication of Sub-0.2${\mu}m$ Multi-level Interconnects
Sub-0.2${\mu}m$ 다층 금속배선 제작을 위한 Cu Dual-dmascene공정 연구
- Chae, Yeon-Sik (Dept. of Electronics Engineering Dongguk University) ;
- Kim, Dong-Il (Dept. of Electronics Engineering Dongguk University) ;
- Youn, Kwan-Ki (Dept. of Electronics Engineering Dongguk University) ;
- Kim, Il-Hyeong (Dept. of Electronics Engineering Dongguk University) ;
- Rhee, Jin-Koo (Dept. of Electronics Engineering Dongguk University) ;
- Park, Jang-Hwan (Dept. of Elec., Hankyong National Univ.)
- 채연식 (東國大學校 電子工學科) ;
- 김동일 (東國大學校 電子工學科) ;
- 윤관기 (東國大學校 電子工學科) ;
- 김일형 (東國大學校 電子工學科) ;
- 이진구 (東國大學校 電子工學科) ;
- 박장환 (國立韓京大學校 電子工學科)
- Published : 1999.12.01
Abstract
In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography,
본 논문에서는 차세대 집적회로의 핵심공정으로 부각되고 있는 CMP를 이용한 Cu Damascene 공정을 연구하였다. E-beam lithography,
Keywords