• ETRI Journal
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• v.32 no.1
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.592-597
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• 2000

In this study (B $a_{0.5}$/S $r_{0.5}$)Ti $O_3$[BST(50/50)] ceramic thin films were prepared by the Sol-Gel method BST(50/50) stock solution was made and spin-coated on the Indium Tin Oxide(ITO)/glass substrate at 4000 rpm for 30 seconds. The coated films were dried at 35$0^{\circ}C$ for 10 minutes and annealed at 650~75$0^{\circ}C$ for 1 hour. The microstructural properties of the BST(50/50) thin film were studied by the XRD and AFM. The ferroelectric perovskite phase was formed at the annealing condition of 75$0^{\circ}C$ for 1 hour. Dielectric constant and loss of this thin were 370, 3.7% at room temperature respectively. The polarization switching voltage showed the good value of 3V. The leakage current density of the BST(50/50) thin film was 10$^{-7A}$c $m^2$with applied voltage of 1.5V. BST(50/50) thin film capacitors having good dielectric and electrical properties are expecting for the application to the dielectric material of DRAM.RAM.M.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.343-346
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• 2004

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.101-101
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• 2003

Al 박막의 화학증착(CVD)과 Al-Cu 합금박막의 물리증착(PVD)을 조합하는 CVD-PVD Al 공정은 수평방향의 배선과 수직방향의 via를 동시에 형성할 수 있으므로 공정단순화 및 생산원가절감 측면에서 장점이 있어서 DRAM 둥의 반도체 소자의 배선공정으로 매우 유망하다[1]. 본 연구에서는 CVD-PVD Al 공정을 이용하여 초고집적소자의 Al via와 Al 배선을 동시에 형성할 때 층간절연막의 영향을 조사하고 그 원인을 규명하였다. Al CVD를 위한 원료기체로는 dimethylaluminum hydride [($CH_3$)$_2$AlH]를 사용하였고 PVD는 38$0^{\circ}C$에서 실시하였다 층간절연막에 따른 CVD-PVD Al의 via hole 매립특성을 조사한 결과, high-density plasma(HDP) CVD oxide의 경우에는 via hole 매립특성이 우수하였으나, hydrogen silscsquioxane (HSQ)의 경우에는 매립특성이 우수하지 않아서 via 저항이 불균일 하였다. 이는 via 식각 후 wet cleaning 과정에서 HSQ에 흡수된 수분이 lamp를 이용한 degassing 공정에 의해서 완전히 제거되지 않아 CVD-PVD 공정 중에 탈착되어 Al reflow에 나쁜 영향을 미치기 때문으로 판단된다. CVD-PVD 공정 전에 40$0^{\circ}C$, $N_2$ 분위기에서 baking하여 HSQ 내의 수분을 충분히 제거함으로써 via 매립특성을 향상시킬 수 있었다. CVD-PVD Al 공정은 aspect ratio 10:1 이상의 via hole도 완벽하게 매립할 수 있었고 이에의해 제조된 Al 배선은 기존의 W plug 공정에 의해 제조된 배선에 비해 낮은 via 저항을 나타내었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.171-171
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• 2003

공정기술의 향상으로 DRAM(dynamic random acess memory)의 고집적화가 이루어지고 있으며, 각 개별소자 및 셀 영역의 점유면적의 감소가 요구되어지고 있다. 따라서 기존에 사용하던 NO (Si$_3$N$_4$/SiO$_2$)박막보다 유전율이 높은 고유전물질에 대한 연구가 진행되고 있다. Ta$_2$O$_{5}$, $Y_2$O$_3$, HfO$_2$, ZrO$_2$,Nb$_2$O$_{5}$, BaTiO$_3$, SrTiO$_3$ 및 (BaSr)TiO등이 고유전물질로 연구되고 있는데 그 중 공정의 안정성, 누설전류의 우수성으로 인해 Ta$_2$O$_{5}$이 많이 연구되고 있다. 본 실험에서는 TiO$_2$가 8 mol%가 첨가된 Ta$_2$O$_{5}$의 열처리 온도에 따른 전기적, 유전특성을 살펴보려고 한다살펴보려고 한다

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.42-45
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• 2001

The high permittivity are applied to DRAM and FRAM. (Ba,Sr)$TiO_3$ (EST) thin films were prepared by Sol-Gel method. BST solution was made and spin-coated on $Pt/SiO_2/Si$ substrate at 4000 [rpm] for 10 seconds in a time coating. Coated specimens were dried at $90[^{\circ}C]$ for 5 minutes. Coating process was repeated from 3 times to 5 times and then sintered at $750[^{\circ}C]$ for 30 minutes. Each specimen was analyzed structure and electrical characteristics. Thickness of BST ceramics thin films are about 2600-2800[$\AA$] in 3 times. Dielectric constant of thin films was little decreased at 1[KHz]~1[MHz]. Dielectric constant and loss to frequency were 250 and 0.02 in BST3. The property of leakage current was stable When the applied voltage was 0~3[V] Leakage current was $10^{9}\sim10^{11}$[A] at 0~3[V].

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.5
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• pp.33-39
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• 1998

The BST (Ba$_{1-x}$ Sr$_{x}$TiO$_{3}$)(50/50) thin film has been grown by RF magnetron reactive sputtering and its characteristics such as crystallization, surface roughness, and electrical properties have been investigated with varying the film thickness. The crystallization and surface roughness of BST thin film are investigated by using XRD and AFM, respectively The BST thin film anealed at 800.deg. C for 2 min has pure perovskite structure and good surface roughness of 16.1.angs.. We estimate that the thickness and dielectric constant of interface layer between BST film and electrode are 3nm and 18.9, respectively, by measuring the capacitance with various film thickness. As the film thickness increases form 80nm to 240nm, the dielectric constant at 10kHz increases from 199 to 265 and the leakage current density at 200kV/cm decreases from 0.682.mu.A/cm$^{2}$ to 0.181 .mu.A/cm$^{2}$. In the case of 240nm-thick BST thin film, the charge storage density and leakage current density at 5V are 50.5fC/.mu.m$^{2}$ and 0.182.mu.A/cm$^{2}$, respectively. The values indicate that the BST thin film is a very useful dielectric material for the DRAM capacitor.or.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.34-40
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• 2012

We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.