• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Ceramist
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• v.4 no.1
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• pp.5-13
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• 2001

차세대 ULSI 소자의 다층금속배선을 위한 저유전 물질중에서, 기존의 절연막인 TEOS-$SiO_2$ 증착 장비 및 공정을 최대한 이용할 수 있으며, 물성 또한 TEOS oxide와 유사하다는 점에서 적용 시점을 앞당길 수 있는 SiOF 박막과 SiOC 박막의 특성에 대해 고찰해 보았다. 1세대 저유전 물질이라 할 수 있는 SiOF는 후속공정에도 안정적인 상태의 박막을 얻기 위해서는 3.0이하의 유전상수를 얻는 것이 불가능한 반면, SiOC는 3.0 이하의 유전상수를 가지는 안정적인 박막을 얻을 수 있다. SiOC 물질은 저밀도의 단일물질로서, 물질 내부에 후속공정에 영향을 미칠만한 기공을 포함하지 않기 때문에 후속 CMP 공정에 적합하였으며, $450^{\circ}C$이하의 열 공정에서도 응력변화 및 박막성분 탈착이 거의 일어나지 않는 점 또한 SiOC 박막의 우수한 후속공정 적합성을 보여주는 결과였다. 이러한 결과를 종합하여 볼 때, 현재 사용되고 있는 1세대 저유전 물질인 SiOF 박막을 대체할 차세대 저유전 물질로 SiOC 물질이 유망하며, 이는 3.0 이하의 유전상수를 요구하는 Gb DRAM 소자나 보다 빠른 동작속도가 생명인 논리회로(logic circuit) 소자에 적용될 경우 큰 소자특성 개선이 기대된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.80-88
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• 1999

In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.145-150
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• 1995

PZT thin films were fabricated on Pt/Ti/SiO2/Si substrates at $500^{\circ}C$ by ECR-PECVD for the application to the charge storage capacitor of ULSI DRAMs. Perovskite single phase PZT films were obtained by controling the film compositional ratio Pb/(Zr+Ti) close to 1. The anion concentrations in the PZT films were successfully controlled by adjusting the flow rates of each MO sources. Capacitance of a typical 94 nm thick PZT film prepared at $500^{\circ}C$ in this work was about 5.3 uF/$\textrm{cm}^2$, which corresponds to the equivalent SiO2 thickness of 0.65nm.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.609-611
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• 2006

This paper describes a CMOS sub-bandgap reference using Pseudo-Resistors which can be widely used in flash memory, DRAM, ADC and Power management circuits. Bandgap reference circuit operates weak inversion for reducing power consumption and uses Pseudo-Resistors for reducing the chip area, instead of big resistor. It is implemented in 0.35um Standard 1P4M CMOS process. The temperature coefficient is 5ppm/$^{\circ}C$ from $40^{\circ}C$ to $100^{\circ}C$ and minimum power supply voltage is 1.2V The core area is 1177um${\times}$617um. Total current is below 2.8uA and output voltage is 0.598V at $27^{\circ}C$.