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http://dx.doi.org/10.9708/jksci.2020.25.04.001

Dynamic Rank Subsetting with Data Compression  

Hong, Seokin (School of Computer Science and Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.25, no.4, 2020 , pp. 1-9 More about this Journal
Abstract
In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.
Keywords
Memory System; DRAM; Data Compression; Performance; Power;
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1 Justin Meza, Mehul A. Shah, Parthasarathy Ranganathan, Mike Fitzner, and Judson Veazey, "Tracking the power in an enterprise decision support system," Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, pp. 261-266, New York, USA, 2009. DOI: 10.1145/1594233.1594295
2 H. David, E. Gorbatov, U. R. Hanebutte, R. Khanna and C. Le, "RAPL: Memory power estimation and capping," Proceedings of the 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 189-194, Austin, USA, 2010. DOI: 10.1145/1840845.1840883
3 Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, and Zhichun Zhu, "Mini-rank: Adaptive DRAM architecture for improving memory power efficiency," Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, pp. 210-221, USA, 2008. DOI: 10.1109/MICRO.2008.4771792
4 Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi, "Rethinking DRAM design and organization for energy-constrained multi-cores," Proceedings of the 37th annual international symposium on Computer architecture , pp. 175-186, New York, USA, 2010. DOI: 10.1145/1815961.1815983
5 J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich and R. S. Schreiber, "Future scaling of processor-memory interfaces," Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, pp. 1-12, Portland, OR, 2009. DOI: 10.1145/1654059.1654102
6 J. H. Ahn, J. Leverich, R. Schreiber and N. P. Jouppi, "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs," IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 5-8, Jan. 2009. DOI: 10.1109/L-CA.2008.13   DOI
7 A. R. Alameldeen and D. A. Wood, "Frequent pattern compression: A significance-based compression scheme for l2 caches," Dept. Comp. Scie., Univ. Wisconsin-Madison, Tech. Rep, vol. 1500, 2004.
8 A. Shafiee, M. Taassori, R. Balasubramonian and A. Davis, "MemZip: Exploring unconventional benefits from memory compression," 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), pp. 638-649, Orlando, FL, 2014. DOI: 10.1109/HPCA.2014.6835972
9 Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry, "Linearly compressed pages: a low-complexity, low-latency main memory compression framework," Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 172-184, New York, USA, 2013. DOI:10.1145/2540708.2540724
10 G. Pekhimenko, V. Seshadri, O. Mutlu, M. A. Kozuch, P. B. Gibbons and T. C. Mowry, "Base-delta-immediate compression: Practical data compression for on-chip caches," 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 377-388, Minneapolis, MN, 2012. DOI: 10.1145/2370816.2370870
11 Somayeh Sardashti and David A. Wood. 2017. Could Compression Be of General Use? Evaluating Memory Compression Across Domains. ACM Trans. Archit. Code Optim. 14, 4, Article 44, 24 pages, 2017. DOI: 10.1145/3138805
12 N. Chatterjee et al., USIMM: The Utah Simulated Memory Module, tech. report UUCS-12-002, Univ. of Utah, 2012.
13 Vinson Young, Prashant J. Nair, and Moinuddin K. Qureshi, "DICE: Compressing DRAM Caches for Bandwidth and Capacity," Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17), pp. 627-638, New York, USA. DOI: 10.1145/3079856.3080243
14 V. Young, S. Kariyappa, and M. Qureshi, "Enabling Transparent Memory-Compression for Commodity Memory Systems," Proceedings of 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 570-581, Washington, USA, 2019. DOI: 10.1109/HPCA.2019.00010
15 Seokin Hong, Bulent Abali, Alper Buyuktosunoglu, Michael B. Healy, and Prashant J. Nair, "Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads," Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '52). Association for Computing Machinery, pp. 453-465, New York, USA, 2019. DOI:10.1145/3352460.3358281
16 Seokin Hong, Prashant J. Nair, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael B. Healy, "Attache: towards ideal memory compression by mitigating metadata bandwidth overheads," Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-51), pp. 326-338, 2018. DOI:10.1109/MICRO.2018.00034