• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.98-103
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• 2008

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.124-130
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• 1989

For the higher density DRAM'S, innovations in fabrication process and circuit design which have led to dramatic density improvement are discussed from the desinger's perspective. A new dynamic RAM cell called Trench Epitaxial Transistor Cell(TETC) using trench technics and SEG have been developed for use in future megabit DRAMS. Storge electrode with $n^+$-polysilicon and $n^+$-source electrode are self-contacted in TETC. With keeping the storage capacitance large enough to prevent soft errors, the cell size reduced to 30% compare with existing BSE cell by utilizing the vertical capacitor made along the isolation region.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.648-657
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• 1995

정보처리의 다양화, 고속화를 위하여 장래의 집적회로는 다량의 정보를 단시간에 처리하지 않으면 안된다. 종래, 3년에 4배의 고집적화가 실현되어 LSI개발에 기술 견인차의 역할을 하고 있는 DRAM(Dynamic Random Access Memory)은 미세화기술의 한계를 우려하면서도 오히려 개발에 박차를 가하고 있다. 이러한 DRAM의 미세, 대용량화에는 미세가공 기술, 새로운 메모리 셀과 트랜지스터 기술, 새로운 회로 기술, 그 이외에 재료박막기술, Computer aided design/Design automation(CAD/DA) 기술, 검사평가기술 혹은 소형팩키지(package)기술등의 광범위한 기술발전이 뒷받침되어 왔다. 그 중에서 미세가공 기술 및 새로운 트랜지스터 기술과 메모리 셀 기술을 중심으로 개발 동향을 살펴보고 최근에 발표된 1Gbit DRAM의 시제품 기술에 대하여 분석해 보기로 한다.

• Ceramist
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• v.9 no.4
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• pp.7-14
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• 2006

• Proceedings of the Korean Vacuum Society Conference
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• 1996.02a
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• pp.36-37
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• 1996

• Electrical & Electronic Materials
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• v.26 no.2
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• pp.32-39
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• 2013

• Korean Journal of Materials Research
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• v.10 no.9
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• pp.607-611
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• 2000

Zr modified $(Ba_{1-x},Sr_x)TiO_3$ thin films as capacitor for high density DRAM were deposited by r.f. magnetron sputtering. The films deposited at various chamber pressure exhibited a polycrystalline structure. The Zr/Ti ratio of the films increased significantly with decreasing the chamber pressure and this variation affected the microstructure and surface roughness of films When chamber pressure increased dielectric constant of the films effected due to decrease of Zr. The thin films prepared in this study show dielectric constant of 380 to 525 at 100KHz. The variation of capacitance and polarization measured as a function of bias voltage suggested that all films were paraelectric phases. Leakage current exhibited smaller value as chamber pressure decrease and the leakage current density of the films deposited above 10mTorr was $10^{-7}~10^{-8}A/cm^2$ order at 200kV/cm. $(Ba_{1-x},Sr_x)(Ti_{1-y},Zr_y)O_3$ thin films in this study appeared to be potential thin film capacitor for high density DRAM.

• Korean Journal of Materials Research
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• v.1 no.4
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• pp.229-235
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• 1991

A new electrode material for $Ta_2O_5$ capacitor was developed to obtain both high dielectric constant and improved electrical properties for use in DRAM. High leakage current and low breakdown field of as-deposited $Ta_2O_5$ film on Si is due to the reduction of $Ta_2O_5$ by silicon at $Ta_2O_5$/electrode interface. $Dry-O_2$ anneal improves the electrical properties of $Ta_2O_5$ capacitor with Si electrode, but it thickens the interfacial oxide and lowers the dielectric constant, subsequently. $Ta_2O_5$ capacitor with TiN exectrode shows better electrical properties and higher dielectric constant than post heat treated $Ta_2O_5$ film on Si. No interfacial oxide layer at $Ta_2O_5$/TiN interface suggests that there\`s no Interaction between $Ta_2O_5$ and electrode. TiN is a adequate electrode material for $Ta_2O_5$ capacitor.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.138-144
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• 1995

It is commonly believed that high permittivity materials will be necessary for future high density Gbit DRAMs. In a first part, we explain the choice of SrTiO3 by ECR MOCVD for Gbit-scale DRAMs. In a second part, after describing the ECR MOCVD system and presenting the requirements SrTiO3 thin films should meet for use in Gbit-scale DRAMs, the physical and electrical properties of srTiO3 thi film prepared by ECR MOCVD are then studied. A stacked capacitor technology, suitable for use in 1 Gbit DRAM, and comprising high permittivity SrTiO3 thin films prepared by ECR MOCVD at $450^{\circ}C$ on electron beam and RIE patterned RuO2/TiN storage nodes is finally described.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.5
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• pp.417-422
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• 2001

The needs of new materials that substitute Si Oxide capacitor layer in high density DRAM increase. So in this paper, we choose the slim region 14/50/50 PLZT composition and fabricated thin films by PLD and estimated the characteristics for DRAM application. 14/50/50 PLZT thin films have crystallized into perovskite structure in the $600^{\circ}C$ deposition temperature and 200 mTorr Oxygen pressure. In this condition, PLZT thin films had 985 dielectric constant, storage charge density 8.17 $\mu$C/$\textrm{cm}^2$ and charging time 0.20ns. Leakage Current density was less than 10$^{-10}$ A/$\textrm{cm}^2$ until 5V bias voltage.