• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.22-22
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• 1997

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• The Korean Journal of Ceramics
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• v.3 no.3
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• pp.213-217
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• 1997

In this paper, the imparct of X-ray and plasma process-induced-damages to La doped Lead Zirconate Titanate (PLZT, (Pb1-xLa)(Zr0.5Ti0.5)O3) capacitor characteristics have been investigated from the viewpoint of gigabit scale dynamic random access memory (DRAM) applications. Plamsa damage causes asymmetric degradation on hysteresis characteristics of PLZT films. On the other hand, X-ray damage results in a symmetrical reduction of charge storage densities (Qc's) for both polarities. As La concentration increases in the films, the radiation hardness of PLZT films on X-ray and plasma exposures is improved. It is observed that the damaged devices are fully recovered by thermal annealing under oxygen ambient.

• Journal of KIISE
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• v.42 no.1
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• pp.107-113
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• 2015

In a database system, updates on pages that are made by a transaction should be stored in a secondary storage before the commit is complete. Generic secondary storages have volatile DRAM caches to hide long latency for non-volatile media. However, as logs that are only written to the volatile DRAM cache don't ensure durability, logging latency cannot be hidden. Recently, a flash SSD with capacitor-backed DRAM cache was developed to overcome the shortcoming. Storage devices, like those with a non-volatile cache, will increase transaction throughput because transactions can commit as soon as the logs reach the cache. In this paper, we analyzed performance in terms of transaction throughput when the SSD with capacitor-backed DRAM cache was used as log storage. The transaction throughput can be improved over three times, by committing right after storing the logs to the DRAM cache, rather than to a secondary storage device. Also, we showed that it could acquire over 73% of the ideal logging performance with proper tuning.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.15-19
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• 2011

The performance of the DRAM is strongly dependent on the purity and surface roughness of the TIT (TiN/Insulator/ TiN) capacitor electrodes. Hence, in the present study, we evaluate the effects of organic contamination and change of surface roughness on the cylindrical TIT capacitor electrodes during the wet cleaning process by various analytical techniques such as TDMS, AFM, XRD and V-SEM. Once the sacrificial oxide and PR (Photo Resist) are removed by HF, the organic contamination and surface oxide films on the bottom Ti/TiN electrode become visible. With prolonged HF process, the surface roughness of the electrode is increased, whereas the amount of oxidized Ti/TiN is reduced due to the HF chemicals. In the 80nm DRAM device fabrication, the organic contamination of the cylindrical TIT capacitor may cause defects like SBD (Storage node Bridge Defect). The SBD fail bit portion is increased as the surface roughness is increased by HF chemicals reactions.

• 전기의세계
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• v.38 no.4
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• pp.24-35
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• 1989

최근 DRAM 시장을 주도하고 잇는 일본의 유수업체의 DRAM cell의 면적과 대비한 축전용량과의 관계로 한눈에 알 수 있다. 1M DRAM급에서 얻었던 Cs값을 확보하면서 Chip Size를 줄이기 위해서는 Cell Size가 축소 되어야 하며 이에 따른 Active Region의 감소를 만회하기 위해서는 3차원 구조를 가지는 Trench나 Stacked cell의 등장이 불가피하게 된것이다. 따라서, 본고에서는 추후로 기억소자의 고집적화에 따라 필수적으로 요구되는 이러한 3차원 Capacitor형성기술의 특징을 알아보고 그 문제점에 대해 살펴보고자 한다.

• 전기의세계
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• v.46 no.4
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• pp.22-27
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• 1997

DRAM(Dynamic Randum Access Memory)은 반도체 소자 중 가장 대표적인 기억소자로, switch 역할을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고 집적화에 용이하다는 이점을 바탕으로, super-computer에서 가전제품, 통신기기 및 산업기기에 이르기까지 널리 이용되어 왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기 시장 진입을 위하여 초기에의 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락 등이 심하여, 시한내에 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성을 가지고 있다. 이러한 관점 때문에 새로운 DRAM 기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-half-micron 이하의 DRAM세대로 갈수록 그에 대한 새로운 기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화 및 저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 애닿 breadthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇 가지 중요한 item을 설정하여 논의하여 보기로 한다.

• Electrical & Electronic Materials
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• v.9 no.4
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• pp.336-343
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• 1996

We have studied the preparation and the properties of $Ba_{1-x}$Sr$_{x}$TiO$_{3}$(BST) thin films by using the sol-gel method. Through the comparison of the effects of various solvents and additives in making solutions, we establish the production method of the stable solution which generates the high quality of BST film. We also set up the heat-treatment conditions for depositing the BST thin film through the TGA and XRD analyses. Through the comparison of the surface conditions of BST films deposited on Pt/Ta/SiO$_{2}$/Si and Pt/Ti/SiO$_{2}$/Si substrates, we find that Ta is more efficient diffusion barrier of Si than Ti so that Ta layer prevents the formation of hillocks. We fabricate the planar type capacitor and measure the dielectric properties of the BST thin film deposited on the Pt/Ta/SiO$_{2}$/Si substrate. Dielectric constant and dielectric loss tangent at 1V, 10kHz, and leakage current density at 3V of the BST thin film are 339, 0.052 and 13.3.mu.A/cm$^{2}$, respectively.ely.