• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.

• Journal of The Korean Society of Integrative Medicine
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• v.7 no.3
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• pp.61-69
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• 2019

Purpose : The purpose of this study was to investigate the effects of Straight leg lifts (SLL) and double leg lowering (DLL) exercise on abdominal muscle activity, visual analog scale (VAS), and flexibility in patients with chronic low back pain (LBP). Methods : A total of 30 LBP patients were divided into two groups: those with SLL exercise group 15 (male=8, female=7) and those with DLL exercise group 15 (male=7, female=8). Before the intervention, the abdominal muscle activity, VAS, and flexibility were measured. After 4 weeks of intervention, the above variables were measured in the same way. The SLL exercise bends the leg $45^{\circ}$ in the supine position, and the DLL exercise was performed as opposed to SLL. At this time, the pressure biofeedback unit (PBU) was placed behind the lumbar to reduce the instability of the pelvis and muscles. The subjects were instructed to use the PBU to maintain the target pressure determined (40 mmHg) during the exercise. Results : The external oblique (EO), internal oblique (IO), and transverse abdominis (TrA) were significantly different in the SLL and DLL group, and EO, IO, and TrA activity improved more significantly increased in the DLL than SLL group (p<.05). The results on the VAS and flexibility were significantly different both group (p<.05). However, there was no significant difference between the groups (p>.05). Conclusion : SLL and DLL exercises in patients with LBP were able to confirm the increased activity of the abdominal muscles, decreased pain, and increased flexibility of the waist. In addition, DLL exercise is more effective in patients with LBP in terms of muscle activity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.857-864
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• 1998

The infuluence of Doppler effects on the tracking performance of a noncoherent second-order delay locked loop (DLL) operating on a data modulated signal is investigated. For the perfoermance analysis we consider the tracking accuracy (steady state error and jitter) of the linear DLL and the reliability of the nonlinear loop. The nonlinear analysis concerning the loop reliability makes use of an asympototic expansion for the MTLL(mean time to lose lock) which has been derived by applying the singular perturbation method. In particular, we give optimal loop parameters and the optimal bandwidth of the bandpass filter in the loop arms to achieve a maximum MTLL. Since Doppler effects can be producesd comparatively in LEO system, we can espect the more reliable DLL loop design. by using the results of the circuit simulation, the delay lock loop is synthesized in FPGA, and verified to get the GPS data from the STR-2770 GPS simulator system. So, the synthesized logic circuit is shown be accurately performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.693-695
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• 2016

A random and systematic jitter suppressed DLL is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.251-259
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• 2000

As a server dependency for the availability and scalability becomes very important, the need for solid server providing non-stop workload have been increased. So, this paper describes a server configuration method for the availability and scalability. For the validity check of this paper, socket application and cluster resource DLL and administration DLL for the application are implemented and tested. 8y relocating the individual failed services from one sewer to another with the microsoft cluster sewer, it was confirmed the feasibility. The result showed that allowed applications on the original server to continue running, unaffected by the failed service.