JSTS:Journal of Semiconductor Technology and Science

  • 제16권1호
  • /
  • Pages.143-146
  • /
  • 2016
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

  • 투고 : 2015.10.18
  • 심사 : 2016.01.22
  • 발행 : 2016.02.28
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

키워드

참고문헌

  1. M. Demirkan, et al, "A pulse-based ultra-wideband transmitter in 90-nm CMOS for WPANs," IEEE J. Solid-State Circuits, 43, No. 12, pp. 2820-2828, 2008 https://doi.org/10.1109/JSSC.2008.2005703
  2. R. Farjad-Rad, et al, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, 37, no. 12, pp. 1804-1812, 2002. https://doi.org/10.1109/JSSC.2002.804340
  3. Q. Du, et al, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE Trans. Circuits Syst. II, Vol. 53, pp. 1205-1209, 2006. https://doi.org/10.1109/TCSII.2006.883103
  4. G. Park, H. Kim, and Jongsun Kim, "A reset-free anti-harmonic anti-harmonic programmable MDLLbased frequency multiplier", J. Semiconductor Technology and Science, Vol. 13, no. 5, pp. 459-464, Oct. 2013. https://doi.org/10.5573/JSTS.2013.13.5.459
  5. S. Han, J. Kim, and Jongsun Kim, "Programmable fractional-ratio frequency multiplying clock generator", IET Electronics Letters, Vol. 50, no. 3, pp. 163-165, 2014. https://doi.org/10.1049/el.2013.2857

피인용 문헌

  1. A 2–4 GHz fast-locking frequency multiplying delay-locked loop vol.14, pp.2, 2017, https://doi.org/10.1587/elex.13.20161056