• Title/Summary/Keyword: DC gain

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A Study on Design of Optimal Satellite-Tracking Antenna $H{\infty}$ Control System (최적 위성추적 안테나 $H{\infty}$ 제어 시스템의 설계에 관한 연구)

  • Kim, Dong-Wan;Jeong, Ho-Seong;Hwang, Hyun-Joon
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.19-30
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    • 1997
  • In this paper we design the optimal satellite-tracking antenna $H{\infty}$ control system using genetic algorithms. To do this, we give gain and dynamics parameters to the weighting functions and apply genetic algorithms with reference model to the optimal determination of weighting functions and design parameter ${\gamma}$ that are given by Glover-Doyle algorithm which can design $H{\infty}$ controller in the state space. These weighting functions and design parameter ${\gamma}$ are optimized simultaneously in the search domain guaranteeing the robust stability of closed-loop system. The effectiveness of this satellite-tracking antenna $H{\infty}$ control system is verified by computer simulation.

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Design of a V Band Power Amplifier Using 65 nm CMOS Technology (65 nm CMOS 공정을 이용한 V 주파수대 전력증폭기 설계)

  • Lee, Sungah;Cui, Chenglin;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.4
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    • pp.403-409
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    • 2013
  • In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

A 5-Gb/s Continuous-Time Adaptive Equalizer (5-Gb/s 연속시간 적응형 등화기 설계)

  • Kim, Tae-Ho;Kim, Sang-Ho;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.14 no.1
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    • pp.33-39
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    • 2010
  • In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

A High Speed CMOS Arrayed Optical Transmitter for WPON Applications (WPON 응용을 위한 고속 CMOS어레이 광트랜스미터)

  • Yang, Choong-Reol;Lee, Sang-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.6
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    • pp.427-434
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    • 2013
  • In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.

Fabrication of Electrostatic Track-Following Microactuator for Hard Disk Drive Using SOI (SOI를 이용한 하드 디스크 드라이브용 정전형 트랙 추적 마이크로 액추에이터의 제작)

  • Kim, Bong-Hwan;Chun, Kuk-Jin;Seong, Woo-Kyeong;Lee, Hyo-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.8
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    • pp.1-8
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    • 2000
  • We have achieved a high aspect ratio track-following microactuator (TFMA) which is capable of driving 0.3 ${\mu}m$ magnetic head for hard disk drive (HDD). it was fabricated on silicon on insulator (SOI) wafer with 20 ${\mu}m$ trick active silicon and 2 ${\mu}m$ thick thermally grown oxide and piggyback electrostatic principle was used for driving TFMA. The first vibration mode frequency of TFMA was 18.5 kHz which is enough for a recording density of higher than 10 Gb/in$^2$. Its displacement was 1.4 ${\mu}m$ when 15 V dc bias plus 15 V ac sinusoidal driving input was applied and its electrostatic force was 50 N. The fabricated actuator shows 7.51 dB of gain margin and 50.98$^{\circ}$ of phase margin for 2.21 kHz servo-bandwidth.

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A 60-GHz LTCC SiP with Low-Power CMOS OOK Modulator and Demodulator

  • Byeon, Chul-Woo;Lee, Jae-Jin;Kim, Hong-Yi;Song, In-Sang;Cho, Seong-Jun;Eun, Ki-Chan;Lee, Chae-Jun;Park, Chul-Soon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.229-237
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    • 2011
  • In this paper, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented. The 60 GHz modulator is designed in a 90-nm CMOS process. The modulator uses a current reuse technique and only consumes 14.4-mW of DC power in the on-state. The measured data rate is up to 2 Gb/s. The 60 GHz OOK demodulator is designed in a 130nm CMOS process. The demodulator consists of a gain boosting detector and a baseband amplifier, and it recovers up to 5 Gb/s while consuming low DC power of 14.7 mW. The fabricated 60 GHz modulator and demodulator are fully integrated in an LTCC SiP with 1 by 2 patch antenna. With the LTCC SiP, 648 Mb/s wireless video transmission was successfully demonstrated at wireless distance of 20-cm.

A Fully-integrated Ku/K Broadband Amplifier MMIC Employing a Novel Chip Size Package (새로운 형태의 CSP를 이용한 완전 집적화 Ku/K밴드 광대역 증폭기 MMIC)

  • Yun, Young
    • Journal of Navigation and Port Research
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    • v.27 no.2
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    • pp.217-221
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    • 2003
  • In this work, we used a novel RF-CSP to develop a broadband amplifier MMIC, including all the matching and biasing components, for Ku and K band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. STO (SrTiO$_3$) capacitors were employed to integrate the DC biasing components on the MMIC. A pre-matching technique was used for the gate input and drain output of the FETs to achieve a broadband design for the amplifier MMIC. The amplifier CSP MMIC exhibited good RF performance (Gain of 12.5$\pm$1.5 dB, return loss less than -6 dB, PldB of 18.5$\pm$1.5 dBm) over a wide frequency range. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the Ku/K band.

Design and Fabrication of a Wide Band and Multi-Resonation Planar Antenna (광대역 다중공진 평판 안테나 설계 및 구현)

  • Lee, Hyeon-Jin;Park, Seong-Il;Lim, Yeong-Seog
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.12
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    • pp.171-176
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    • 2005
  • This study designed and fabricated a multi-purpose planar antenna for base stations that are accessible to DCS, WiBro, and ISM. The proposed antenna was designed into an open loop form from the existing monopole structure. The capacitance of the multi-purpose antenna was increased by the coupling of open parts. This makes the use of MMIC and LTCC convenient and the antenna is smaller and has a larger gain than existing antennas. The resonance distance and bandwidth can be adjusted by changing the open gap and the height of the loop of the antenna. The bandwidth of the designed antenna satisfies DCS, IMT-2000, WiBro, Bluetooth, wireless LAN and ISM bands based on VSWR 2. The entire frequency bandwidth is $58.75\%$ of $1.575GHz\~2.985GHz(1.41GHz)$. Also, the radiation pattern of the antenna displayed co-polarization and cross-polarization characteristics at 1.6GHz, 2.3GHz and 2.8GHz.

A Capacitorless Low-Dropout Regulator With Enhanced Response Time (응답 시간을 향상 시킨 외부 커패시터가 없는 Low-Dropout 레귤레이터 회로)

  • Yeo, Jae-Jin;Roh, Jeong-Jin
    • Journal of IKEEE
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    • v.19 no.4
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    • pp.506-513
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    • 2015
  • In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

A Very Compact 60 GHz LTCC Power Amplifier Module (초소형 60 GHz LTCC 전력 증폭기 모듈)

  • Lee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.11 s.114
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    • pp.1105-1111
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    • 2006
  • In this paper, using low-temperature co-fired ceramic(LTCC) based system-in-package(SiP) technology, a very compact power amplifier LTCC module was designed, fabricated, and then characterized for 60 GHz wireless transmitter applications. In order to reduce the interconnection loss between a LTCC board and power amplifier monolithic microwave integrated circuits(MMIC), bond-wire transitions were optimized and high-isolated module structure was proposed to integrate the power amplifier MMIC into LTCC board. In the case of wire-bonding transition, a matching circuit was designed on the LTCC substrate and interconnection space between wires was optimized in terms of their angle. In addition, the wire-bonding structure of coplanar waveguide type was used to reduce radiation of EM-fields due to interconnection discontinuity. For high-isolated module structure, DC bias lines were fully embedded into the LTCC substrate and shielded with vias. Using 5-layer LTCC dielectrics, the power amplifier LTCC module was fabricated and its size is $4.6{\times}4.9{\times}0.5mm^3$. The fabricated module shows the gain of 10 dB and the output power of 11 dBm at P1dB compression point from 60 to 65 GHz.