• Title/Summary/Keyword: DC bias current

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The Laser Range Finder for the Mobile Robot Navigation using a Lock-in Amplifier

  • Yoon, Hee-Sun;Shin, Myung-Kwan;Park, Kyi-Hwan
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1423-1426
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    • 2005
  • Map building is the most important thing for the mobile robots navigation. It requires specific vision system such as CCD camera, range finding system, and many other things. Laser range finder has highly collimated beams can be obtained easily, thus achieving lateral resolution. Laser Diode is used for a continuous laser source. The Automatic Current Control Circuit and the Bias-T is used for mix AC signal with DC bias. This signal is used for driving Laser Diode. The main idea of the calculating distance is detecting phase shift between reference signal and detected signal by photo detector. For the signal processing, the Lock-in amplifier system is addressed in this paper. We used a diffused reflected beam to detect phase shift in this system. But this beam is minuteness signal so it can be easily buried in nose. Lock-in amplifier is used to measure the amplitude and phase of signals which are buried in noise.

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Cross Sectional Thermal and Electric Potential Imaging of an Operating MOSFET (작동중인 모스 전계 효과 트랜지스터 단면에서의 상대온도 및 전위 분포 측정)

  • Kwon, Oh-Myoung
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.27 no.7
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    • pp.829-836
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    • 2003
  • Understanding of heat generation in semiconductor devices is important in the thermal management of integrated circuits and in the analysis of the device physics. Scanning thermal microscope was used to measure the temperature and the electric potential distribution on the cross-section of an operating metal-oxide-semiconductor field-effect transistor (MOSFET). The temperature distributions were measured both in DC and AC modes in order to take account of the leakage current. The measurement results showed that as the drain bias was increased the hot spot moved to the drain. The density of the iso-potential lines near the drain increased with the increase in the drain bias.

Hot-carrier Induced MOSFET Degradation and its Lifetime Measurement (Hot-carrier 효과로 인한 MOSFET의 성능저하 및 동작수명 측정)

  • 김천수;김광수;김여환;김보우;이진효
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.2
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    • pp.182-187
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    • 1988
  • Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

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Design of a Rceiver MMIC for the CDMA Terminal (CDMA 단말기용 수신단 MMIC 설계)

  • 권태운;최재하
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.1
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    • pp.65-70
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    • 2001
  • This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

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The Optimization of SONOSFET SPICE Parameters for NVSM Circuit Design (NVSM 회로설계를 위한 SONOSFET SPICE 파라미터의 최적화)

  • 김병철;김주연;김선주;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.5
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    • pp.347-352
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    • 1998
  • In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

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Simulated DC Characteristics of AlGaN/GaN HEMls with Trench Shaped Source/Drain Structures (트렌치 구조의 소스와 드레인 구조를 갖는 AlGaN/GaN HEMT의 DC 출력특성 전산모사)

  • Jung, Kang-Min;Lee, Young-Soo;Kim, Su-Jin;Kim, Dong-Ho;Kim, Jae-Moo;Choi, Hong-Goo;Hahn, Cheol-Koo;Kim, Tae-Geun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.10
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    • pp.885-888
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    • 2008
  • We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

Performance of Passive Boost Switched Reluctance Converter for Single-phase Switched Reluctance Motor

  • Ahn, Jin-Woo;Lee, Dong-Hee
    • Journal of Electrical Engineering and Technology
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    • v.6 no.4
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    • pp.505-512
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    • 2011
  • A novel passive boost power converter forsingle-phaseswitched reluctance motor is presented. A simple passive circuit is proposed comprisingthree diodes and one capacitor. The passive circuitis added in the front-end of a conventional asymmetric converter to obtain high negative bias. Based on this passive network, the terminal voltage of the converter side is a general DC-link voltage level in parallel mode up to a double DC-link voltage level in series mode. Thus,it can suppress the negative torque generation from the tail current and improve the output power. The results of the comparative simulation and experiments forthe conventional and proposed converter verify the performance of the proposed converter.

Circuit-Level Reliability Simulation and Its Applications (회로 레벨의 신뢰성 시뮬레이션 및 그 응용)

  • 천병식;최창훈;김경호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.1
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    • pp.93-102
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    • 1994
  • This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

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The DC Characteristics of Submicron MESFEFs (서브미크론 MESFET의 DC 특성)

  • 임행상;손일두;홍순석
    • Electrical & Electronic Materials
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    • v.10 no.10
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    • pp.1000-1004
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    • 1997
  • In this paper the current-voltage characteristics of a submicron GaAs MESFET is simulated by using the self-consistent ensemble Monte Carlo method. The numerical algorithm employed in solving the two-dimensional Poisson equation is the successive over-relaxation(SOR) method. The total number of employed superparticles is about 1000 and the field adjusting time is 10fs. To obtain the steady-state results the simulation is performed for 10ps at each bias condition. The simulation results show the average electron velocity is modified by the gate voltage.

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A Study on Developement of CuN/Cu/CuN Electrode Material for PDP (PDP용 CuN/Cu/CuN 전극재료의 개발에 관한 연구)

  • Cho, J.S.;Park, C.H.;Sung, Y.M.;Jeong, S.S.;Seok, B.Y.;Ryu, J.Y.;Kim, J.H.
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1572-1575
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    • 1996
  • A new type $Cu_{x}N/Cu/Cu_{x}N$ thin film electrode material with high adhesion to glass was developed by the dc reactive planar magnetron sputtering system for the PDP(Plasma Display Panel). The adhesive force of the $Cu_{x}N$ thin film was in the range of $20{\sim}40(N)$ under the conditions of the $N_2$ partial pressure of 15%, discharge current of 70mA, discharge voltage of 450V and substrate bias voltage of -100V. The adhesive force was depended on the $N_2$ partial pressure, discharge current and substrate bias voltage.

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