• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.246-251
• /
• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.17 no.4
• /
• pp.217-228
• /
• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.117-120
• /
• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.1
• /
• pp.219-224
• /
• 2017

Recently, the importance of DRAM is very significant not only in embedded systems and mobile devices but also in high-end modern microprocessors and multicore processors. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the microprocessor performance. In this paper, a microprocessor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the microprocessor performance has been evaluated.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.3
• /
• pp.203-208
• /
• 2017

Recently, the importance of DRAM is very significant in multicore processors which are widely used in computers, laptops, tablet PCs, and mobile devices. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the multicore processor performance. In this paper, a multicore processor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the multicore processor performance has been evaluated.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.9A
• /
• pp.931-939
• /
• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.3
• /
• pp.177-183
• /
• 2018

Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06a
• /
• pp.196-198
• /
• 2006

Shader architecture is one of the fastest growing fields in the ever advancing 3D graphics, and massive amounts of Ideas and technologies are being introduced to the market continuously. In this paper, we present a flexible cycle-accurate simulation environment to accelerate and alleviate the process of developing and verifying these ideas and technologies. Combination of 3D graphics API and hardware simulator allows OpenGL applications to be emulated off-the-shelf for a given shader micro-architecture. Easily modified parameters allow the simulation environment to be tailored to specific demands or requirements.

• Journal of Power Electronics
• /
• v.15 no.4
• /
• pp.1018-1025
• /
• 2015

This paper proposes a methodological scheme for the photovoltaic (PV) simulator design. With the advantages of a digital controller system, linear interpolation is proposed for precise fitting with higher computational efficiency. A novel control strategy that directly tackles two different duty cycles is proposed and implemented to achieve a full-range operation including short circuit (SC) and open circuit (OC) conditions. Systematic design procedures for both hardware and algorithm are explained, and a prototype is built. Experimental results confirm an accurate steady state performance under different load conditions, including SC and OC. This low power apparatus can be adopted for PV education and research with a limited budget.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.11
• /
• pp.1021-1030
• /
• 2010

In the sensor network, many tiny nodes construct Ad-Hoc network using wireless interface. As this type of system consists of thousands of nodes, managing each sensor node in real world after deploying them is very difficult. In order to install the sensor network successfully, it is necessary to verify its software using a simulator beforehand. In fact Sensor network simulators require high fidelity and timing accuracy to be used as a design, implementation, and evaluation tool of wireless sensor networks. Cycle-accurate, instruction-level simulation is the known solution for those purposes. In this paper, we developed an instruction-level sensor network simulator for Telos sensor node as named TeloSlM. It consists of MSP430 and CC2420. Recently, Telos is the most popular mote because MSP430 can consume the minimum energy in recent motes and CC2420 can support Zigbee. So that TeloSlM can provide the easy way for the developers to verify software. It is cycle-accurate in instruction-level simulator that is indispensable for OS and the specific functions and can simulate scalable sensor network at the same time. In addition, TeloSlM provides the GUI Tool to show result easily.