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Design of an Automatic Generation System for Cycle-accurate Instruction-set Simulators for DSP Processors  

Hong, Sung-Min (서강대학교 전자공학과 대학원 CAD & ES연구실)
Park, Chang-Soo (서강대학교 전자공학과 대학원 CAD & ES연구실)
Hwang, Sun-Young (서강대학교 전자공학과 대학원 CAD & ES연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.32, no.9A, 2007 , pp. 931-939 More about this Journal
Abstract
This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.
Keywords
MDL; DSP; ASIP; Automatic Generation; Instruction-set Simulator;
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