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http://dx.doi.org/10.7236/JIIBC.2018.18.3.177

Effects Analysis of DRAM for Digital Signal Processor Performance  

Lee, Jongbok (Dept. of Electronic & Information Eng., Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.18, no.3, 2018 , pp. 177-183 More about this Journal
Abstract
Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.
Keywords
DRAM; digital signal processor; performance;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 L. J. Karam, I. AlKamal, A. Gatherer, G. A. Frantz, D. V. Anderson, B. L. Evans, "Trends in Multi-core DSP Platforms," IEEE Signal Processing Magazine, pp. 1-10, Nov. 2009
2 P. Rosenfeld et al. "DRAMSim2: A Cycle Accurate Memory System Simulator," IEEE Computer Architecture Letters, 2011.
3 Y. Kim et al. "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA, 2012.
4 D. Lee et al. "Tiered-Latency DRAM : A Low Latency and Low Cost DRAM Architecture," HPCA, 2013.
5 C. G. Lee, "UTDSP Benchmark," http://www.eecg.toronto.edu/-corinna/DSP/infrast ructure/UTDSP.html, May 1998.
6 Y. Kim, W. Yang, and O. Mutlu, "Ramulator : A Fast and Extensible DRAM Simulator," IEEE Computer Architecture Letters, 2015.
7 J. Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 12, no. 3, pp. 9-13, Jun. 2012.   DOI
8 T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, Vol. 35, No. 2, pp. 59-67, Feb. 2002.   DOI
9 JEDEC, JESD79-3 DDR3 SDRAM Standard, Jun. 2007.