• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.700-702
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• 2005

The most electrical apparatus should be able to withstand short-time current and peak current during a specified short time until circuit breakers have interrupted fault current. It defines the short-time withstand ability of electric a apparatus to be remain for a time interval under high fault current conditions. It is specified by both dynamic ability and thermal capability. KERI(Korea Electrotechlology Research Institute) recently constructed the new short-time current and low voltage short circuit testing facilities. This paper shows short- circuit calculation of transformer and describes high current measuring system, and evaluate the result of short-time withstand test used in $3{\phi}$ 90MVA short-time current testing facilities.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.443-449
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• 2010

Current testing is an effective method which offers higher fault detection and diagnosis capabilities than voltage testing. Since current testing requires much longer testing time than voltage testing, it is important to note that a fault is untestable if the two nodes have same values at all times. In this paper, we present an object oriented fault detection scheme for various fault models using current testing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults and its usefulness in various fault models.

• Journal of the Korean Society for Nondestructive Testing
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• v.5 no.2
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• pp.49-52
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• 1986

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.2
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• pp.155-159
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• 2016

Eddy current testing (ECT) is an important nondestructive testing technology for the inspection of flaws in conductive materials. However, this widely used technology is not suitable for inspecting lamination when a conventional pancake coil is used because the eddy current (EC) generated by the pancake coil is parallel to the lamination and will not be perturbed. A new method using a rectangular coil placed vertical to the work piece is proposed for lamination detection. The vertical sections of the rectangular coil induce ECs that are vertical to the lamination and can be perturbed by the lamination. A parametric study of a rectangular coil by finite element analysis was performed in order to examine the capability of generating vertical EC.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.4
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• pp.258-267
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• 2015

Eddy current testing is widely used for inspecting steam generator tubing in nuclear power plants (NPPs). The inspection technique for steam generator tubing in NPPs should be qualified in accordance with examination guidelines. When the components of a qualified system such as eddy current tester, probe, and data analysis program, are changed, the equivalency of the modified system to the originally qualified system must be verified. The eddy current tester is the most important part of an eddy current testing system because it excites and transmits alternating currents to the probe, receives coil impedance of the probe and generates signals for anomalies. The Korea Hydro & Nuclear Power Co., Ltd. (KHNP) developed an eddy current testing system with an eddy current tester and data acquisition-analysis program for inspecting the steam generator tubing in NPPs; this system can be used for an array probe and as a bobbin and rotating probes. The equivalency assessment for the currently developed system was carried out, and we describe the results in this paper.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.9 no.1
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• pp.40-47
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• 2013

The capacity factor of nuclear power plant in Korea is the highest level in the world. However, the integrity assessment of nuclear power plant is depended on foreign country. Especially, most eddy current testing systems for inspecting steam generators in nuclear power plant are currently imported from USA, Canada, and so on. Therefore, the eddy current testing system can react more active and adaptive from economic and managerial standpoint for actual nuclear power plants in Korea is required. In this paper, an eddy current testing system for inspecting steam generators in nuclear power plants is introduced. Frequency generator, analog circuit, analog digital converter circuit, and digital control circuit are composed in eddy current testing system. A benchmarking of acquisition system and acquisition software, eddynet 11i made by Zetec, and modifications are carried out based on the test environment of Korea nuclear power plants. Finally, all eddy current apparatus are integrated to inspect steam generator tubes in nuclear power plants.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.6
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• pp.524-530
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• 2008

The spin valve tunneling magnetoresistance (SV-TMR) sensor performance is analyzed using Stoner-Wohlfarth model for the detection of eddy current signals in nondestructive testing applications. The SV-TMR response in terms of the applied AC magnetic field dominantly generates the second harmonic amplitude in hard axis direction. The second harmonic eddy current signal detection using SV-TMR sensor shows higher performance than that of the coil sensor at lower frequencies. The SV-TMR sensor with high sensitivity gives a good solution to improve the low frequency performance in comparison with the inductive coil sensors. Therefore, the low frequency eddy current techniques based on SV-TMR sensors are specially useful in the detection of hidden defects, and it can be applied to detect the deeply embedded flaws or discontinuities in the conductive materials.

• ETRI Journal
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• v.23 no.2
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• pp.77-84
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• 2001

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.