• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.62-68
• /
• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.11
• /
• pp.83-94
• /
• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.15-22
• /
• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.231-234
• /
• 2002

A transceiver for ADSL systems contains an interpolated combfilter, halfband filters, oversampling sigma delta modulator, a current steering DAC and an analog filler. The circuit complexity of the architecture makes it necessary to use behavioral models to determine the system features. For this reason, we need a specific behavioral simulation environment using the Matlab program. The Matlab is crucial for these circuits to be rapidly incorporated in larger systems, in particular in the context of mixed-signal-test schemes. Design trade-off among the blocks has also been discussed. The design methodology is based on behavioral design and CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.4
• /
• pp.1-9
• /
• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.4
• /
• pp.871-876
• /
• 2011

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V-$0.18{\mu}m$ CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.609-612
• /
• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.4
• /
• pp.381-388
• /
• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.57-65
• /
• 2002

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.