• Journal of Electrical Engineering and Technology
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• 제6권1호
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• pp.48-58
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• 2011

In this paper, an attempt has been made to design the current and speed proportional and integral (PI) regulators of self-commutating current source inverter-fed induction motor drive having capacitors at the machine end and to investigate the transient performance of the same for step changes in reference speed. The mathematical model of the complete drive system is developed in closed loop, and the characteristic equations of the systems are derived using perturbation about steady-state operating point in order to develop the characteristic equations. The D-partition technique is used for finding the stable region in the parametric plane. Frequency scanning technique is used to confirm the stability region. Final selection of the regulator parameters is done by comparing the transient response of the current and speed loops for step variations in reference. The performance of the drive is observed analytically through MATLAB simulation.

• Journal of Power Electronics
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• 제5권2호
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• pp.151-159
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• 2005

The errors generated from current measurement paths are inevitable, and they can be divided into two categories: offset error and scaling error. The current data including these errors cause periodic speed ripples which are one and two times the stator electrical frequency respectively. Since these undesirable ripples bring about harmful influences to motor driving systems, a compensation algorithm must be introduced to the control algorithm of the motor drive. In this paper, a new compensation algorithm is proposed. The signal of the integrator output of the d-axis current regulator is chosen and processed to compensate for the current measurement errors. Usually the d-axis current command is zero or constant to acquire the maximum torque or unity power factor in the ac drive system, and the output of the d-axis current regulator is nearly zero or constant as well. If the stator currents include the offset and scaling errors, the respective motor speed produces a ripple related to one and two times the stator electrical frequency, and the signal of the integrator output of the d-axis current regulator also produces the ripple as the motor speed does. The compensation of the current measurement errors is easily implemented to smooth the signal of the integrator output of the d-axis current regulator by subtracting the DC offset value or rescaling the gain of the hall sensor. Therefore, the proposed algorithm has several features: the robustness in the variation of the mechanical parameters, the application of the steady and transient state, the ease of implementation, and less computation time. The MATLAB simulation and experimental results are shown in order to verify the validity of the proposed current compensating algorithm.

• ETRI Journal
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• 제42권5호
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.353-355
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• 2007

A simple technique for PFC circuit is presented using UC3854. This technique is about current peak controlling by a reference current generator. Decreased peak currents of the boost pre-regulator reduce circuit current stress and so rated currents of circuit elements are minimized. Simulation and experimental results will verify the viability of the new scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.244-246
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• 2001

In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.

• 전기의세계
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• 제15권5호
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• pp.32-39
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• 1966

This voltage Regulator, which regulates voltage in different way from the conventional regulator, is constructed by circular-plate core type stators and controllers (are similar to rotor of conventional). The principle of this Voltage Regulator is based on the rotating magnetic field theory including peculiar homopolar and heteropolar concept. Comparing with the conventional induction regulator, this regulator need not to have short windings and can cancel armature reaction. Moreover, it is able to decrease the machine noise and control the phase of it freely. And it's efficiency can become more than 95% which almost the same as that of transformer's. By increasing numbers of cores of the same size, the output power can be increased, the insulation can be decreased and high Voltage can directly be connected because applied voltage is distributed to each core. This Voltage Regulator can be also used as a current regulator, a starter a induction motor and a phase transformer etc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• 한국산업정보학회논문지
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• 제21권1호
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• pp.1-6
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• 2016

본 논문에서는 기생 트랜지스터를 억제하여 대기 전류를 낮춰 기동전류를 개선한 수직 PNP 트랜지스터의 특성을 소개한다. 기생 효과를 억제하기 위해, 회로 변경 없이 "DN+ 링크"를 사용하여 기생 PNP 트랜지스터를 억제 시킨 수직 PNP 트랜지스터를 설계하였으며, 표준 IC 프로세서를 이용한 LDO 레귤레이터를 제작했다. 제작된 기생 PNP 트랜지스터의 hFE 가 기존의 18에서 0.9로 감소하였다. 개선된 "DN+ 링크" 구조 수직 PNP 트랜지스터로 제작된 LDO 레귤레이터의 기동 전류는 기존의 기동 전류 90mA에서 32mA 로 감소되었다. 이로 인해 대기상태에서 저 소비전력을 구현한 LDO 레귤레이터를 개발하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.522-524
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• 2018

A New Direct AC LED Driver has been proposed for wide output power range and precise constant current regulation using an advanced auto commutation topology. The conventional shunt regulation method provides a stepped input current shape by fixed regulation references in the linear regulator of the each channel, which results in poor current regulation and high THD. The conventional method needs to assign a linear regulator in each LED channel so that the number of linear regulator increases when extending the number of channels especially at high power application. The proposed regulation method can drive multiple switches to regulate each LED channel current by a single amplifier with sinusoidal reference so that large number of LED channel can be simply extended with less BOM cost and low THD is obtained with the accurate current regulation thanks to the sinusoidal input current control in the closed loop control. To confirm the validity of the proposed circuit, theoretical analysis and experimental results from a 20-W LED driver prototype are presented.

• 대한전기학회논문지
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• 제33권2호
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• pp.76-82
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• 1984

This paper presents the design and the optimal control method of current-fed half-brige switching regulator. To achieve fast response load current variation is fed to control input, and simple optimal control model has been derived with provision of current control loop in the control circuit. Test results show that the control system model is correct and 5ms response time has been obtained at 25 KHz switching frequency.