A Compensation Method for Time Dealy of Full Digital Synchronous Frame Current Regulator of PWM ac Drives

디지털 동기좌표계 전류제어기에서의 시지연을 고려한 PWM 기법

In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.