• 센서학회지
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• 제21권1호
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• 한국재료학회지
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• 제20권8호
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• pp.434-438
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• 2010

The selenization process has been a promising method for low-cost and large-scale production of high quality CIGS film. However, there is the problem that most Ga in the CIGS film segregates near the Mo back contact. So the solar cell behaves like a $CuInSe_2$ and lacks the increased open-circuit voltage. In this study we investigated the Ga distribution in CIGS films by using the $Ga_2Se_3$ layer. The $Ga_2Se_3$ layer was applied on the Cu-In-Ga metal layer to increase Ga content at the surface of CIGS films and to restrict Ga diffusion to the CIGS/Mo interface with Ga and Se bonding. The layer made by thermal evaporation was showed to an amorphous $Ga_2Se_3$ layer in the result of AES depth profile, XPS and XRD measurement. As the thickness of $Ga_2Se_3$ layer increased, a small-grained CIGS film was developed and phase seperation was showed using SEM and XRD respectively. Ga distributions in CIGS films were investigated by means of AES depth profile. As a result, the [Ga]/[In+Ga] ratio was 0.2 at the surface and 0.5 near the CIGS/Mo interface when the $Ga_2Se_3$ thickness was 220 nm, suggesting that the $Ga_2Se_3$ layer on the top of metal layer is one of the possible methods for Ga redistribution and open circuit voltage increase.

• 마이크로전자및패키징학회지
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• 제26권3호
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• pp.81-88
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• 2019

본 연구에서는 그래핀 산화(graphene oxide, GO) 분말 첨가가 ball grid array(BGA) 패키지와 printed circuit board(PCB)간 Sn-3.0Ag-0.5Cu(SAC305) 무연솔더 접합부의 electromigration(EM) 수명에 미치는 영향에 대하여 보고 하였다. 솔더 접합 직후, Ni/Au표면처리된 패키지 접합계면에서는 $(Cu,Ni)_6Sn_5$가 생성되었으며 organic solderability preservative(OSP) 표면처리 된 PCB 접합계면에서는 $Cu_6Sn_5$ 금속간화합물(intermetallic compound, IMC)이 생성되었다. $130^{\circ}C$, $1.0{\times}10^3A/cm^2$ 전류밀도 하에서 EM 수명평가 결과, GO를 첨가하지 않은 솔더 접합부의 평균 파괴 시간은 189.9 hrs으로 도출되었고, GO를 첨가한 솔더 접합부의 평균 파괴 시간은 367.1 hrs으로 도출되었다. EM에 의한 손상은 패키지 접합계면에 비하여 pad 직경이 작은 PCB 접합계면에서 전자 유입에 의한 Cu의 소모로 인하여 발생하였다. 한편, 첨가된 GO는 하부계면의 $Cu_6Sn_5$ IMC와 솔더 사이에 분포하는 것을 확인하였다. 따라서, SAC305 무연솔더에 첨가된 GO가 전류 집중 영역에서 Cu의 빠른 확산을 억제하여 우수한 EM 신뢰성을 갖는 것으로 생각된다.

• Applied Science and Convergence Technology
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• 제23권1호
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• pp.14-26
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• 2014

Copper is an important component from coin metal to electronic wire, integrated circuit, and to lithium battery. Copper oxides, mainly including $Cu_2O$ and CuO, are important semiconductors for the wide applications in solar cell, catalysis, lithium-ion battery, and sensor. Due to their low cost, low toxicity, and easy synthesis, copper oxides have received much research interest in recent year. Herein, we review the crystallization of copper oxides by designing various chemical reaction routes, for example, the synthesis of $Cu_2O$ by reduction route, the oxidation of copper to $Cu_2O$ or CuO, the chemical transformation of $Cu_2O$ to CuO, the chemical precipitation of CuO. In the designed reaction system, ligands, pH, inorganic ions, temperature were used to control both chemical reactions and the crystallization processes, which finally determined the phases, morphologies and sizes of copper oxides. Furthermore, copper oxides with different structures as electrode materials for lithium-ion batteries were also reviewed. This review presents a simple route to study the reaction-crystallization-performance relationship of Cu-based materials, which can be extended to other inorganic oxides.

• Korean Chemical Engineering Research
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• 제48권5호
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• pp.654-659
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• 2010

박막형 유기 태양전지의 효율 향상을 위하여 정공 수송층인 CuPc 층에 p형 유기 반도체인 rubrene을 함량 별로 도핑하여 ITO/PEDOT:PSS/CuPc: rubrene/CuPc:C60(blending ratio 1:1)/C60/BCP/Al의 이종접합구조를 가지는 p-i-n형 유기 박막형 태양전지 소자를 제조한 후, 유기 태양전지의 전류 밀도-전압(J-V) 특성, 단락 전류($J_{sc}$), 개방 전압($V_{oc}$), 충진 인자(fill factor:FF), 에너지 전환 효율(${\eta}_e$) 등을 측정하고 계산하여 성능 평가를 수행 하였다. 정공 수송층으로 사용된 CuPc 층에 rubrene을 도핑함으로써 에너지 흡수 스펙트럼에서 흡수 강도가 감소하였다. 그러나 CuPc 보다 큰 밴드갭을 가지며 높은 정공 이동도를 가지는 결정성 rubrene의 도핑에 의해 제조된 p-i-n형 유기 박막 태양전지의 성능은 향상 되는 것으로 확인되었다. 제조된 유기 태양전지의 에너지 전환 효율(${\eta}_e$)은 1.41%로 실리콘 태양전지와 비교해서 아직도 성능 향상을 위한 많은 노력이 필요함을 보여 준다.

• 마이크로전자및패키징학회지
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• 제23권2호
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• pp.73-78
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• 2016

집적회로(Integrated Circuit) 소자의 트랜지스터(transistor) 밀도 증가는 소자에서 발생하는 열 방출(heat dissipation)의 급격한 상승을 초래하여 열 문제를 발생시키고, 이는 소자의 성능과 열적 신뢰성에 영향을 크게 미친다. 열문제의 해결방안 중 본 연구에서는 냉매를 이용한 액체 냉각방법을 연구하였으며, 실리콘 웨이퍼에 관통실리콘비아(through Si via)와 마이크로 채널(microchannel)을 딥 반응성 이온 애칭(deep reactive ion etching)로 구현한 후 유리기판과 어노딕본딩을 통하여 액체 냉각 구조를 제작하였다. 제작된 마이크로 채널 위에 Ag, Cu 또는 Cr/Au/Cu bump를 스크린프린팅(screen printing) 방법으로 형성하였고, 범프의 유무를 통해 액체 냉각 전후의 냉각 모듈의 실리콘 표면온도의 변화를 적외선현미경으로 분석하였다. Cr/Au/Cu bump가 탑재된 액체 냉각 모듈의 경우 가열온도 $200^{\circ}C$에서 냉각 전후의 실리콘 표면 온도 차이는 약 $45.2^{\circ}C$이고, 전력밀도 감소는 약 $2.8W/cm^2$ 이었다.

• 한국재료학회지
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• 제24권2호
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• pp.105-110
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• 2014

The aim of this work was to investigate the effects of electrodeposition conditions on the microstructural characteristics of copper thin films. The microstructure of electroplated Cu films was found to be highly dependent on electrodeposition conditions such as system current and current density, as well as the bath solution itself. The current density significantly changed the preferred orientation of electroplated Cu films in a DC system, while the solution itself had very significant effects on microstructural characteristics in a pulse-reverse pulse current system. In the DC system, polarization at high current above 30 mA, changed the preferred orientation of Cu films from (220) to (111). However, Cu films showed (220) preferred orientation for all ranges of current density in the pulse-reverse pulse current system. The grain size decreased with increasing current density in the DC system while it remained relatively constant in the pulse-reverse pulse current system. The sheet resistance increased with increasing current density in the DC system due to the decreased grain size.

• 한국재료학회지
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• 제26권2호
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• pp.84-89
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• 2016

We present the rectifying and nitrogen monoxide (NO) gas sensing properties of an oxide semiconductor heterostructure composed of n-type zinc oxide (ZnO) and p-type copper oxide thin layers. A CuO thin layer was first formed on an indium-tin-oxide-coated glass substrate by sol-gel spin coating method using copper acetate monohydrate and diethanolamine as precursors; then, to form a p-n oxide heterostructure, a ZnO thin layer was spin-coated on the CuO layer using copper zinc dihydrate and diethanolamine. The crystalline structures and microstructures of the heterojunction materials were examined using X-ray diffraction and scanning electron microscopy. The observed current-voltage characteristics of the p-n oxide heterostructure showed a non-linear diode-like rectifying behavior at various temperatures ranging from room temperature to $200^{\circ}C$. When the spin-coated ZnO/CuO heterojunction was exposed to the acceptor gas NO in dry air, a significant increase in the forward diode current of the p-n junction was observed. It was found that the NO gas response of the ZnO/CuO heterostructure exhibited a maximum value at an operating temperature as low as $100^{\circ}C$ and increased gradually with increasing of the NO gas concentration up to 30 ppm. The experimental results indicate that the spin-coated ZnO/CuO heterojunction structure has significant potential applications for gas sensors and other oxide electronics.

• ETRI Journal
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• 제45권5호
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• 한국전기전자재료학회논문지
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• 제29권6호
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• pp.365-369
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• 2016

In this paper, we fabricated Cu/Mn alloy shunt resistor with low resistance and thermal stability for use of mobile electronic devices. We designed metal alloy composed of copper (Cu) and manganese (Mn) to embody in low resistance and low TCR which are conflict each other. Cu allows high electrical conductivity and Mn serves thermal stability in this Cu/Mn alloy system. We confirmed the elemental composition of the designed metal alloy system by using energy dispersive X-ray (EDX) analysis. We obtained low resistance below $10m{\Omega}$ and low temperature coefficient of resistance (TCR) below $100ppm/^{\circ}C$ from the designed Cu/Mn alloy resistor. And in order to minimize resistance change caused by alternative frequency on circuit, shape design of the metal alloy wire is performed by rolling process. Finally, we conclude that design of the metal alloy system was successfully done by alloying Cu and 3 wt% of Mn, and the Cu/Mn alloy resistor has low resistance and thermal stability.