• Korean Journal of Materials Research
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• v.17 no.9
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• pp.484-488
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• 2007

Mo(Ti) alloy and pure Cu thin films were subsequently deposited on $SiO_2-coated$ Si wafers, resulting in $Cu/Mo(Ti)/SiO_2$ structures. The multi-structures have been annealed in vacuum at $100-600^{\circ}C$ for 30 min to investigate the outdiffusion of Ti to Cu surface. Annealing at high temperature allowed the outdiffusion of Ti from the Mo(Ti) alloy underlayer to the Cu surface and then forming $TiO_2$ on the surface, which protected the Cu surface against $SiH_4＋NH_3$ plasma during the deposition of $Si_3N_4$ on Cu. The formation of $TiO_2$ layer on the Cu surface was a strong function of annealing temperature and Ti concentration in Mo(Ti) underlayer. Significant outdiffusion of Ti started to occur at $400^{\circ}C$ when the Ti concentration in Mo(Ti) alloy was higher than 60 at.%. This resulted in the formation of $TiO_2/Cu/Mo(Ti)\;alloy/SiO_2$ structures. We have employed the as-deposited Cu/Mo(Ti) alloy and the $500^{\circ}C-annealed$ Cu/Mo(Ti) alloy as gate electrodes to fabricate TFT devices, and then measured the electrical characteristics. The $500^{\circ}C$ annealed Cu/Mo($Ti{\geq}60at.%$) gate electrode TFT showed the excellent electrical characteristics ($mobility\;=\;0.488\;-\;0.505\;cm^2/Vs$, on/off $ratio\;=\;2{\times}10^5-1.85{\times}10^6$, subthreshold = 0.733.1.13 V/decade), indicating that the use of Ti-rich($Ti{\geq}60at.%$) alloy underlayer effectively passivated the Cu surface as a result of the formation of $TiO_2$ on the Cu grain boundaries.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.115-119
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• 2000

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.20-20
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• 1997

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.11a
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• pp.129-129
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• 1998

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.503-508
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• 1999

We have investigated the physical and diffusion barrier property of Ti-Si-N film for Cu metallization. The ternary compound was deposited by using reactive rf magnetron sputtering of a TiSi$_2$target in an Ar/$N_2$gas mixture. Resistivities of the films were in range of 358$\mu$$\Omega$-cm, to 307941$\mu$$\Omega$-cm, and tended to increase with increasing the $N_2$/Ar flow rate ratio. The crystallization of the Ti-Si-N compound started to occur at 100$0^{\circ}C$ with the phases of TiN and Si$_3$N$_4$identified by using XRD(X-ray Diffractometer). The degree of the crystallization was influenced by the $N_2$/Ar flow ratio. The diffusion barrier property of Ti-Si-N film for Cu metallization was determined by AES, XRD and etch pit by secco etching, revealing the failure temperature of 90$0^{\circ}C$ in 43~45at% of nitrogen content. In addition, the very thin compound (10nm) with 43~45at% nitrogen content remained stable up to $700^{\circ}C$. Furthermore, thermal treatment in vacuum at $600^{\circ}C$ improved the barrier property of the Ti-Si-N film deposited at the $N_2$(Ar+$N_2$) ratio of 0.05. The addition of Ti interlayer between Ti-Si-N films caused the drastic decrease of the resistivity with slight degradation of diffusion barrier properties of the compound.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2003.05a
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• pp.88-88
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• 2003

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.27-33
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• 2000

The selective chemical vapor deposition techniques for Cu metallization were studied. For enhancing the selectivity, furnace annealing and N$_{2}$ plasma were treated on patterned TiN/BPSG prior to the copper deposition. As a result, Cu did not deposited lead to suppressing the nucleation on BPSG singificantly. With the increasement the plasma treatment temperature, copper nucleation on BPSG was suppressed mote effectively, From TOF-SIMS(Time-of-Flight Secondary ion Mass Spectrometry), it is considered that annealing and N$_{2}$ plasma treatment remove hydroxyl(0-H) group so that eliminating the nucleation site for copper precursor enhance the selectivity.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.65-69
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• 2010

In this study, we investigated the effects of UBM(Under Bump Metallization) and solder composition on the drop impact reliability of wafer level packaging. Fan-in type WLP chips were prepared with different solder ball composition (Sn3.0Ag0.5Cu, and Sn1.0Ag0.5Cu) and UBM (Cu 10 ${\mu}m$, Cu 5 ${\mu}m$\Ni 3 ${\mu}m$). Drop test was performed up to 200 cycles with 1500G acceleration according to JESD22-B111. Cu\Ni UBM showed better drop performance than Cu UBM, which could be attributed to suppression of IMC formation by Ni diffusion barrier. SAC105 was slightly better than SAC305 in terms of MTTF. Drop failure occurred at board side for Cu UBM and chip side for Cu\Ni UBM, independent of solder composition. Corner and center chip position on the board were found to have the shortest drop lifetime due to stress waves generated from impact.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.403-406
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• 2003

Poyethylene(PE) films could be modified by radiation grafting of N-vinyl pyrollidone(NVP) using radiation. FTIR spectra was used to confirm the modification of PE films. The modified films were activated by one-step or two-step methods for electroless Cu plating. Morphology of metallized films has been investigated. Electroless Cu plating onto the modified films depends mainly on the grafting degree and activation type. The electrical conductivity and adhesion of the metallized films has been investigated and tested in regard of grafting degree of samples.