• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.2
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• pp.55-62
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• 2000

The wetting balance test was performed in an attempt to estimate the wetting properties of the UBM-coated Si-wafer on one side to the Sn-Pb solder. The wetting curves of the one and both side-coated UBM layers had the similar shape and the parameters characterizing the curve shape showed the similar transition tendency to the temperature. The wetting property estimation was possible with the new wettability indices from the wetting curves of one side-coated specimen; $F_{min}$, $F_{s}t_{s}$ and $t_s$. For UBM of Si-chip, Au/Cu/Cr UBM was better than Au/Ni/Ti in the point of wetting time. The contact angle of the one side coated Si-plate to the Sn-Pb solder could be calculated from the force balance equation by measuring the static state force and the tilt angle.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.82-82
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• 2010

표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.2
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• pp.187-192
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• 2011

UBM(Under Bump Metallurgy) is very important for successful realization of Flip-Chip technology. In this study, it is investigated the interfacial reactions between various Sn-Ag solder alloys and Ni-P/Au UBM and Cu plate finish. It is also evaluated the shear strength by using the micro shear-punch test method for Sn-37Pb alloy, binary and ternary alloys of environment-friendly Pb-free solder alloys which are applied in the electronic packages. In terms of interfacial microstructure, the Pb-free solder joints have thicker IMCs than the Sn-Pb solder joints. The thickness of IMC is related to Reflow time. The IMC has been observed to grow with the increase in Reflow time. As a result of the shear test, in case of Max. shear strength, Pb-free solder showed the highest strength value and Sn-37Pb showed the lowest strength value 10 be generally condition of Reflow time.

• Journal of the Korean Society of Industry Convergence
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• v.12 no.4
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• pp.215-219
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• 2009

A packaging technology based on flip-chip bonding and Pb-free solder for silicon pressure sensors on printed circuit board (PCB) is presented. First, the bump formation process was conducted by Pb-free solder. Ag-Sn-Cu solder and the pressed-screen printing method were used to fabricate solder bumps. The fabricated solder bumps had $189-223{\mu}m$ width, $120-160{\mu}m$ thickness, and 5.4-6.9 standard deviation. Also, shear tests was conducted to measure the bump shear strength by a Dage 2400 PC shear tester; the average shear strength was 74 g at 0.125 mm/s of test speed and $5{\mu}m$ shear height. Then, silicon pressure sensor packaging was implemented using the Pb-free solder and bump formation process. The characteristics of the pressure sensor were analogous to the results obtained when the pressure sensor dice are assembled and packaged using the standard wire-bonding technique.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Korean institute of surface engineering
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• v.36 no.5
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• pp.373-378
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• 2003

With increasing environmental concerns, application of lead-free solder and fluxless soldering process have been taken attention from the electronic packaging industry. Plasma treatment is one of the soldering methods for the fluxless soldering, and it can prevent environmental pollution cased by flux. On this study fluxless soldering process under $Ar-H_2$plasma using lead free solders such as Sn-3.5 wt%Ag, Sn-3.5 wt%Ag-0.7 wt%Cu and Sn-37%Pb for a reference was investigated. As the plasma reflow has higher soldering temperature than normal air reflow, the effects of UBM(Under Bump Metallization) thickness on the interfacial reaction and bonding strength can be critical. Experimental results showed in case of the thin UBM, Au(20 nm)/Cu(0.3 $\mu\textrm{m}$)/Ni(0.4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), shear strength of the soldered joint was relatively low as 19-27㎫, and it's caused by the crack observed along the bonded interface. The crack was believed to be produced by the exhaustion of the thin UBM-layer due to the excessive reaction with solder under plasma. However, in case of thick UBM, Au(20 nm)/Cu(4 $\mu\textrm{m}$)/Ni(4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), the bonded interface was sound without any crack and shear strength gives 32∼42㎫. Thus, by increasing UBM thickness in this study the shear strength can be improved to 50∼70%. Fluxed reflow soldering under hot air was also carried out for a reference, and the shear strength was 48∼52㎫. Consequently the fluxless soldering with plasma showed around 65∼80% as those of fluxed air reflow, and the possibility of the $Ar-H_2$ plasma reflow was evaluated.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.231-233
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• 2005

Laser have been utilized as a heat source for the soldering of electronic components for the their capability of localized heating and faster heating rate. Laser soldering process, especially the diode laser soldering of BGA solderball was investigated. In this study, an attempt was made to investigate the possibility of laser soldering using Sn-37Pb and Sn-3Ag-0.5Cu solderball. The laser energy absorbed on the pad raised the temperature of the solderball forming a reflowed solder bump. The result were discussed based on the measurement of pull and shear strength of the bond.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.35-41
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• 2022

In the era of Fifth-Generation (5G), technology requirements such as Artificial Intelligence (AI), Cloud computing, automatic vehicles, and smart manufacturing are increasing. For high efficiency of electronic devices, research on high-intensity circuits and packaging for miniaturized electronic components is important. A solder paste which consists of small solder powders is one of common solder for high density packaging, whereas an electroplated solder has limitation of uniformity of bump composition. Researches are underway to improve wettability through the addition of nanoparticles into a solder paste or the surface finish of a substrate, and to suppress the formation of IMC growth at the metal pad interface. This paper describes the principles of improving the wettability of solder paste and suppressing interfacial IMC growth by addition of nanoparticles.