• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1225-1228
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• 2003

본 논문에서는 Coupling capacitance 변화량이 Static coupling capacitance 값보다 클 수 있다는 것을 새로운 테스트 회로를 이용하여 실험적으로 증명하였다. 테스트 회로는 배선의 지연시간이 배선의 저항보다는 배선의 정전용량에만 의존하도록 하여 배선의 지연시간을 평가함으로써 배선의 정전용량의 변화 즉, Coupling capacitance 의 변화량을 정확히 평가할 수 있도록 하였다. 0.15 ㎛ CMOS 기술을 이용하여 실험한 결과 In-phase crosstalk 인 경우에는 변화량이 Static coupling capacitance 보다 작았지만 Anti-phase 인 경우에는 Static coupling capacitance 보다 크게 나타남을 보여주고 있다. 따라서 배선에 의한 정확한 지연시간 평가를 위해서는 Crosstalk 이 발생한 경우의 Coupling capacitance 변화량을 정확히 반영하는 것이 매우 필요함을 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.47-54
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• 2005

In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, ${\Delta}Cc$ by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that ${\Delta}Cc$ is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk ${\Delta}Cc$ is always larger than Cc while for in-phase crosstalk ${\Delta}Cc$ is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.

• ETRI Journal
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• v.32 no.1
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• pp.68-72
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• 2010

The coupling between the transverse and longitudinal components of the channel electron motion in NMOS devices leads to a reduction in the barrier height. Therefore, this study theoretically investigates the effects of the in-plane velocity of channel electrons on the capacitance-voltage characteristics of nano NMOS devices under inversion bias. Numerical calculation via a self-consistent solution to the coupled Schrodinger equation and Poisson equation is used in the investigation. The results demonstrate that such a coupling largely affects capacitance-voltage characteristic when the in-plane velocity of channel electrons is high. The ballistic transport ensures a high in-plane momentum. It suggests that such a coupling should be considered in the quantum capacitance-voltage modeling in ballistic transport devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.17-24
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• 2004

This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.887-891
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• 2003

In this paper, two filters with center frequency of 19.58MHz were cascaded and its bandwidth characteristics were investigated with the variations of coupling capacitance for intermediate frequency (IF) bandpass filter application. The cascaded filter showed the higher stop region, reduction of spurious response and increase of selectivity. With the increase of coupling capacitance, insertion loss was increased but spurious response reduced. The cascaded filter with coupling capacitance of 15pF showed insertion loss of 5.643dB, 3dB bandwidth of 55.089kHz and 20dB bandwidth of 83.608kHz, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.71-72
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• 2000

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the mutual coupling capacitances present in a pixel. The mutual coupling capacitance causes a pixel voltage error. In this study, semi-empirical model, which is adopted from VLSI interconnection capacitance calculations, is used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and arbitrary given image pattern, the root mean square (RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained this study can be utilized to design the larger area and finer image quality panel.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.2
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• pp.111-116
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• 2016

This paper proposes a high-frequency (MHz) LLC resonant converter for a capacitor coupling wireless power transfer (CCWPT). The CCWPT uses electric field in the coupling capacitor between the transmitter and receiver electrodes with a dielectric layer. Given that capacitance is very small and the impedance is large, transferring power with a simple series resonance is difficult. Therefore, the high frequency (MHz) and high Q factor LLC converter is proposed to reduce the impedance of the coupling capacitance and to obtain a high output voltage. This paper deals with the operation analysis of the proposed LLC converter and a theoretical capacitance estimation. The operation and features of the proposed CCWPT LLC converter is verified with a 4.2 W prototype for charging mobile devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.123-126
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• 2002

A proposed multi-layer ceramic (MLC) chip type band-pass filter (BPF) is presented. The MLC chip BPF has the benefits of low cost and small size. The BPF consists of coulped stripline resonators and coupling capacitors. The BPF is designed to have an attenuation pole at below the passband for a receiver band of IMT-2000 handset. The computer-aided design technology is applied for analysis of the BPF frequency characteristics. The passband and attenuation pole depend the coupling between resonators and coupling capacitance. The frequency characterics of the passband and attenuation pole are analysed with the variance of the coupling between resonators and coupling capacitance. An equivalent circuit and structure of MLC chip BPF are proposed. The frequency characteristics of the BPF is well acceptable for IMT-2000 application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.740-743
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• 2003

A multi-layer ceramic (MLC) chip type band-pass filter (BPF) is presented. The MLC chip BPF has the benefits of low cost and small size. The BPF consists of coulped stripline resonators and coupling capacitors. The BPF is designed to have an attenuation pole at below the passband for a receiver band of IMT-2000 handset. The computer-aided design technology is applied for analysis of the BPF frequency characteristics. The passband and attenuation pole depend on the coupling between resonators and coupling capacitance. The frequency characterics of the passband and attenuation pole are analyzed with the variation of the coupling between resonators and coupling capacitance. An equivanlent circuit and structure of MLC chip BPF are proposed. The frequency characteristics of the BPF is well acceptable for IMT-2000 application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.