• Journal of the Korean Ceramic Society
• /
• v.54 no.1
• /
• pp.66-69
• /
• 2017

In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.

• Journal of information and communication convergence engineering
• /
• v.13 no.3
• /
• pp.189-196
• /
• 2015

In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.5
• /
• pp.424-428
• /
• 2010

This paper describes the design and analysis of AlN piezoelectric micro energy harvester. The harvester was designed to convert ambient vibration energy to electrical power as a AlN piezoelectric material compatible with CMOS (complementary metal oxide semiconductor) process. To cut off the leakage current, AlN was used as the insulating layer. Also, Mo was used for the excellent c-axis crystal growth as the bottom electrode. The AlN harvester which it has the low operating frequency was designed by using the ANSYS FEA (finite element analysis). From the simulation results, the resonance frequency of designed model is about 360 Hz and analyzed the bending mode, displacement and expectation output.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.117-120
• /
• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• Journal of Astronomy and Space Sciences
• /
• v.33 no.3
• /
• pp.229-236
• /
• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• Proceedings of the KSR Conference
• /
• 2009.05a
• /
• pp.900-904
• /
• 2009

The measurement of contact wire uplift in electric railway is one of the most test method to accept the maximum permitted speed of new vehicles or pantographs. The contact wire uplift can be measured for shot periods when pantograph is running in monitoring station. This paper describes the development of two different methods for contact uplift measurement using vision-based system and wireless online monitoring system. Our vision-based system employs a high-speed CMOS (Complementary Metal Oxide Semiconductor) camera with gigabit ethernet LAN. The development of a real-time remote monitoring system that acquires data from any kind of sensor to be transmitted by wireless communication from overhead line and structure at 25 kV to a computer in catenary system. The proposed two kind of different measurement systems to evaluation for dynamic uplift of overhead contact wire shows promising on-field applications for high speed train such as Korea Tilting Train (TTX) and Korea Train eXpress (KTX).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.9
• /
• pp.771-774
• /
• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.235-236
• /
• 2007

CCD(Charge-Coupled Device) 혹은 CMOS (Complementary Metal Oxide Semiconductor)와 같은 소자를 이용하여 빛을 전기적 신호인 Image로 재구성하는 촬상소자(Color Capture Device)는 촬영환경이 어두워지면 Dynamic Range가 작아지고, Noise가 상대적으로 심해진다[1][2]. 본 논문에서는 촬영 환경이 어두울 때, Resolution을 Preserving하는 Pixel Pitch가 큰 촬상 소자와 Motion Blur를 억제하는 Exposure Time이 긴 촬상 소자의 조합을 신호처리로 구현하여, 신호의 Power를 향상시켜 Dynamic Range를 키우고 Noise의 Boost-up을 억제하여 SNR(Signal to Noise Ratio)을 향상시키는 방식으로, 촬상 장치의 감도를 향상시켜 화질을 개선하는 방법을 제안한다.

• ETRI Journal
• /
• v.43 no.5
• /
• pp.900-908
• /
• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• ETRI Journal
• /
• v.42 no.6
• /
• pp.912-921
• /
• 2020

Quantum-dot cellular automata (QCA) is an alternative complementary metal-oxide-semiconductor (CMOS) technology that is used to implement high-speed logical circuits at the atomic or molecular scale. In this study, an optimal 2-to-4 decoder in QCA is presented. The proposed QCA decoder is designed using a new formulation based on the MV32 gate. Notably, the MV32 gate has three inputs and two outputs, which is equivalent two 3-input majority gates, and operates based on cellular interactions. A multilayer design is suggested for the proposed decoder. Subsequently, a new and efficient 3-to-8 QCA decoder architecture is presented using the proposed 2-to-4 QCA decoder. The simulation results of the QCADesigner 2.0.3 software show that the proposed decoders perform well. Comparisons show that the proposed 2-to-4 QCA decoder is superior to the previously proposed ones in terms of cell count, occupied area, and delay.