• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

• Journal of Astronomy and Space Sciences
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• 제18권3호
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• pp.231-238
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• 2001

CMOS (complementary metal oxide semiconductor) 영상센서를 이용한 영상관측 시스템 을 제작하여 천문관측 활용 가능성에 대한 조사를 수행하였다. CCD(charge coupled device) 영상센서는 지난 30여년간 개발을 거듭해온 결과, 대부분의 영상획득장비나 천문관측용으로 사용되는 극미광 영상장비로 사용되왔다. 그러나 CMOS영상센서 가 실용화되면서 CCD를 이용한 극미광 영상관측 시스템과 일반 상용 영상시스템은 CMOS 영상센서로 교체되고 있다. CMOS 영상센서의 경우 CCD에 비해 시스템 잡음과 측광 성능은 뒤지지만, 태양과 별의 영상을 얻어본 결과 일반적인 영상관측장비로서는 사용이 가능하다.

• 센서학회지
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 센서학회지
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• 제30권1호
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• 진공이야기
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• 제5권2호
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• pp.18-22
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• 2018

wo dimensional (2D) van der Waals (vdW) nanosheet semiconductors have recently attracted much attention from researchers because of their potentials as active device materials toward future nano-electronics and -optoelectronics. This review mainly focuses on the features and applications of state-of-the-art vdW 2D material devices which use transition metal dichalcogenides, graphene, hexagonal boron nitride (h-BN), and black phosphorous: field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) inverters, Schottky diode, and PN diode. In a closing remark, important remaining issues of 2D vdW devices are also introduced as requests for future electronics and photonics applications.

• 센서학회지
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• 제29권2호
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• 대한기계학회논문집A
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• 제39권1호
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• pp.105-109
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• 2015

고출력 레이저에 의한 영상 센서의 손상 분석 연구를 수행하였다. 고출력 레이저에 의한 금속의 손상에 관한 연구는 많이 이루어져 있지만, 상대적으로 고출력 레이저에 취약한 영상 시스템의 손상 연구는 미비한 상태이다. 본 논문에서는 CMOS 영상 센서에 고출력 레이저가 조사 되었을 때, 영상 센서가 받는 손상에 대해 실험적으로 분석하였다. 고출력 레이저 소스로는 근적외선대역의 연속발진 광섬유 레이저를 사용하였으며, 레이저 세기와 조사시간에 따른 CMOS 영상 센서의 영구적 손상 및 영상 품질을 분석하였다. 그 결과 조사시간과 레이저세기가 증가함에 따라 먼저 색상 손상이 나타나고 이후 작동불능 상태가 되었으며, 이러한 손상은 조사시간보다 레이저 세기에 더 큰 영향을 받는 것으로 나타났다.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.