• The Journal of Korean Association of Computer Education
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• v.21 no.6
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• pp.83-92
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• 2018

The subjective question is appropriate for evaluation of deep thinking, but it is not easy to score. Since, regardless of same scoring criterion, the graders are able to produce different scores, we need the objective automatic evaluation system. However, the system has the problem of Korean analysis and comparison. This paper suggests the Korean syntactic analysis and subjective grading system using the syntactic-semantic tree comparator. This system is the hybrid grading system of word based and syntactic-semantic tree based grading. This system grades the answers on the subjective question using the syntactic-semantic comparator. This proposed system has the good result. This system will be utilized in Korean syntactic-semantic analysis, subjective question grading, and document classification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.219-228
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• 2001

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.1
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• pp.87-94
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• 2008

This paper proposes a high-gain monopulse antenna using the folded reflectarray for a monopulse target-tracking radar systems designed at the center frequency of 94 GHz. In target-tracking radar systems, the angle of arrival of the incoming wave Is determined by comparing the signal received on two or more non-coincident antenna patterns. This is the physical basis of most target-tracking techniques and the comparison is made simultaneously in a monopulse radar systems. In this paper, the antenna consists of polarizing grid, reflectarray, multimode feed horn, and comparator implemented by wavguide. The antenna is able to have three radiation patterns by using the monopulse feed systems assembled by multimode feed horn and comparator. The antenna demonstrates maximum gains 36dB, 33.5dB and 27.2dB at sum mode, azimuth mode, and evevation mode respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.224-227
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• 2016

This paper proposes a design of W-band mm-wave wideband monopulse comparator using waveguide structure for applications. The main idea of proposed design is to combine a self-compensating phase shifter on $90^{\circ}$ hybrid for wideband $180^{\circ}$ hybrid. Using multiple conventional phase shifters, because of their narrow-band characteristics, tends to restrict working bandwidth of system including antennas. Proposed comparator could relieve the problem since it applies the self-compensating phase shifter. The comparator has waveguide structure so it shows excellent characteristic in loss. It also show wideband characteristic in amplitude and phase response between ports.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1035-1037
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• 2001

This paper presents an improved hys- teresis current control method for three-phase PWM power inverters using 3-level comparator. Hysteresis current controller using 3-level comparator has an advantage of constant switching frequency compared with conventional hysteresis current controller. However, this method has disadvantage that the longer sampling period, the larger current error because the switching is performed without considering current error magnitude of each phase. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous hysteresis current control method.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.48-53
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• 1999

We demonstrate small-scale high-T$_c$ superconductor RSFQ(Rapid Single Flux Quantum) circuits using multilayer bicrystal technology. An RSFQ balanced comparator is demonstrated with good current resolution, and its operating conditions are discussed in some detail. A single-loop delta-sigma modulator is realized adding a feedback loop to the comparator. The effect of the feedback is confirmed by dc measurement and simulation. A design of an RSFQ toggle flip-flop with the same multilayer bicrystal technology is suggested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.37-42
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• 2010

A novel hysteresis tunable monolithic comparator circuit based on a $0.35{\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.212-215
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• 1999

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.