• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.46-56
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• 2002

In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.2
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• pp.176-184
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• 2011

As modern megalopolises become more complex and huge, convenience and safety of citizens are main components for a welfare state. In order to make safe society, telemetrics technology, which remotely measures the information of target system using electronic devices, is an essential component. In general, telemetrics technology consists of USN (ubiquitous sensor network) based on a wireless network, smart sensor, and SoC (system on chip). In the smart sensor technology, the following two problems should be overcome. Firstly, because it is very difficult for transducer manufacturers to develop smart sensors that support all the existing network protocols, the smart sensor must be independent of the type of networking protocols. Secondly, smart sensors should be modular so that a faulty sensor element can be replaced without replacing healthy communication element. To solve these problems, this paper investigates the feasibility of an IEEE 1451 based ZigBee smart sensor system. More specifically, a smart sensor for large network coverage has been developed using ZigBee for active telemetrics.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.1-8
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• 1998

This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.12-19
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• 2016

The monitoring system in railway is under study to forecast any derailment and accident by defect of train. Because the monitoring system is composed of wireless sensor network based on ZigBee-communication between inside and outside of train, the study for wireless channel analysis is required. Especially, if multipath delay profile exist in the channel, the equalizer and channel estimator can be required for preventing receiver performance degradation. Therefore, we analyzed the wireless channel in train environment using measured data and, proposed the channel estimation method through the characterisitic of chip code, under the consideration of the channel characteristics in train. To show the performance of proposed method, we demonstrate the performance by mean square error(MSE), computational complexity and bit error rate(BER).

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.45-56
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• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.61-68
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• 2004

Wireless mobile communication systems request high speed mobility and high speed data transmission capability. In order to meet the requirements, OFDM(Orthogonal Frequency Division Multiplex) is mainly adopted in the physical layer of the wireless systems. In commercial wireless mobile systems, IEEE802.(11a, 16e, etc) series seem to be used as the modulation method. For supporting multiple air-interfaces in a wireless mobile system, different kinds of OFDM based modulation methods should be supported in one modem chip. It requires a variable point IFFT/FFT or reconfigurable IFFT/FFT processor. In this paper, we propose the design method of a reconfigurable IFFT/FFT processor. In addition, it is shown that a reconfigurable IFFT/FFT processor can he implemented by using the proposed method.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.67-75
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• 1999

In this paper, we present an ASIC(Application Specific Integrated Circuit) design of wavelet transform filter Wavelet transform is used in lots of application fields which include image compression, because it has an excellent energy compaction. The operation characteristic and performance of wavelet transform filter are analyzed by using verilog-HDL(Hardware Description Language). In this paper, the designed wavelet transform filter uses line memory to improve data processing rate. Generally, when it reads and writes data of DRAM by using Fast Page Mode, input and output processing is very fast in horizontal direction but substantially slow in vertical direction. The use of line memory solves this low speed processing problem. As a result, though the size of the chip is getting larger, processing time for an image frame becomes 4.66ms. Generally, since the limit of 1 frame processing time on the data of TV video is 33ms, so it is appropriate for TV video.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• Korean Parent-Child Health Journal
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• v.10 no.2
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• pp.147-157
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• 2007

Purpose: Assessment of stress and coping effort of hospitalized children's mother are very important factor to support and recover the children. The purpose of this study was to identify the stress and coping effort in mothers whose children are hospitalized. And analyzes the correlation between mother's stress and coping effort on the hospitalized children. Method: This study surveyed 70 mothers whose children are hospitalized. The data was collected for this study at one university hospital in Daejeon from June 1,2007 to July 10, 2007. The instruments used in this study were the mother's stress scale which was developed by Ok-Nam, You(1998), modified by Ho-Jin, Mun(2001), and the mother's coping effort were measured with the Coping Health Inventory for Parents(CHIP) developed by McCubbin and Patterson(1981). The data was analyzed by using SPSS program and include ANOVA, and Pearson's Correlation. Result: The mother's stress was average 2.42 out of a possible 4 points. Type of coping effort was in order of type III(cope with it by understanding medical circumstances)(M=2.73), type I(Cope with it through positive definition)(M=2.43), type II (cope with it by maintaining psychological stability)(M=2.28). Total coping effort according to general character of mothers whose children are hospitalized showed a significant difference in occupation(P<.05). Correlations between mother's stress and total coping effort was r=-.361(P<.05). Conclusion: This study based on nursing of stress and coping effort of hospitalized children's mothers. Pediatric nurses need to establish a stronger communication board and a relationship between medical staff and children's parents so that have supportive information. And to establish a support program that strengthens the coping effort of hospitalized children's mothers.