• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1282-1287
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• 2005

The accuracy of chip alignment in inferior product inspection of COG(Chip On Glass) to be measured a few micro unit is very important role since the accuracy of chip inspection depends on chip alignment. In this paper, we propose the area segmentation pattern matching method to enhance the accuracy of chip alignment. The area segmentation pattern matching method compares, and matches correlation coefficients between the characteristic features within the detailed area and the areas. The three areas of pattern circumference are learned to minimize the matching error by bad pattern. The proposed method has advantage such as reduction of matching time, and enhanced accuracy since the characteristic features are searched within the segmented area.

• ETRI Journal
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• v.33 no.1
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• pp.13-17
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• 2011

A highly miniaturized on-chip $180^{\circ}$ hybrid employing periodic ground strip structure (PGSS) was realized on a silicon radio frequency integrated circuit. The PGSS was placed at the interface between $SiO_2$ film and silicon substrate, and it was electrically connected to top-side ground planes through the contacts. Owing to the short wavelength characteristic of the transmission line employing the PGSS, the on-chip $180^{\circ}$ hybrid was highly miniaturized. Concretely, the on-chip $180^{\circ}$ hybrid exhibited good radio frequency performances from 37 GHz to 55 GHz, and it was 0.325 $mm^2$, which is 19.3% of a conventional $180^{\circ}$ hybrid. The miniaturization technique proposed in this work can be also used in other fields including compound semiconducting devices, such as high electron mobility transistors, diamond field effect transistors, and light emitting diodes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.69-73
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• 2002

We have designed and fabricated a low-cost, V-band CPW receiver chip set using GaAs PHEMT technology for the application of millimeter-wave wireless communication systems. Low noise amplifiers and down-converters were developed for this chip set. The fabricated low noise amplifier showed an S$\sub$21/ gain of 14.9 ㏈ at 60 ㎓ and a noise figure of 4.1 ㏈ at 52 ㎓. The down-converter exhibited a high conversion gain of 2 ㏈ at the low LO Power of 0 ㏈m. This work demonstrates that the GaAs PHEMT technology is a viable low-cost solution for V-band applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• Molecules and Cells
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• v.45 no.2
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• pp.76-83
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• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.

• Annual Conference of KIPS
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.390-391
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• 2022

Recently, SpaceX, private enterprise dealing in space development company, has reported a plan for launching of low earth orbit satellites via Starlink Business, and launched 900 satellites until now. Concretely, it plans tp operate Ku/Ka band satellite, and launch 7,518 of V band satellites for broadband communication. Therefore, wireless communication service for ship will be provided, and various solutions will be offered through the low earth orbit satellites. In this work, we investigated RF characteristics of coplanar waveguide employing periodic 3D coupling structures, and examined its potential for a development of marine radio communication FISoC (fully-integrated system on chip) semiconductor device.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.19-24
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• 2005

This paper presents design simulation, implementation, and measurement of a miniaturized GPS/K-PCS dual-band LTCC chip antenna for mobile communication handsets. The dimension of LTCC chip antenna is $9mm\times15mm\times1.2mm$. The meander type radiating patch for dual-band operation is realized by using via holes with 0.3mm height to connect upper and lower-layer antenna. The lower meander type antenna is to be tuned to the lower frequency (GPS) band. The upper meander antenna with via hole connection is to contribute the higher frequency (K-PCS) band. The resonant frequency and frequency ratio of the proposed antenna can be adjusted by changing the height of via-hole and effective path of meander radiating patch. The electrical characteristics of the meander chip antenna applied to a GPS/K-PCS are suitable for mobile communication application.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.