Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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SEC-DED-DAEC codes without mis-correction for protecting on-chip memories

오정정 없이 온칩 메모리 보호를 위한 SEC-DED-DAEC 부호

  • Received : 2022.09.08
  • Accepted : 2022.09.19
  • Published : 2022.10.31
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Abstract

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

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References

  1. S. Vangal, S. Paul, S. Hsu, A. Agarwal, S. Kumar, R. Krishnamurthy, H. Krishnamurthy, J. Tschanz, V. De, and C. H. Kim, "Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 5, pp. 843-856, May 2021. https://doi.org/10.1109/TVLSI.2021.3061649
  2. A. Haran, N. M. Yitzhak, E. Mazal-Tov, E. Keren, D. David, N. Refaeli, E. Preziosi, R. Senesi, C. Cazzaniga, C. D. Frost, T. Hadas, U. Zangi, and C. Andreani, "Ultralow Power System-on-Chip SRAM Characterization by Alpha and Neutron Irradiation," IEEE Transaction on Nuclear Science, vol. 68, no. 11, pp. 2598-2608, Nov. 2021. https://doi.org/10.1109/TNS.2021.3112622
  3. H. Li, L. Xiao, C. Qi, and J. Li, "Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets," IEEE Transaction on Circuits and Systems-I, vol. 68, no. 10, pp. 4170-4180, Oct. 2021. https://doi.org/10.1109/TCSI.2021.3100900
  4. V. Bandeira, I. Oliveira, F. Rosa, R. Reis, and L. Ost, "An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack," IEEE Transaction on Circuits and Systems-II, vol. 68, no. 1, pp. 446-450, Jan. 2021. https://doi.org/10.1109/TCSII.2020.3011367
  5. S. Lin and D. Costello, Error Control Coding, 2nd ed. Pearson, 2004.
  6. A. Dutta and N. A. Touba, "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code," in Proceeding of the 25th IEEE VLSI Test Symposium, Berkeley: CA, USA, pp. 349-354, 2007.
  7. M. Richter, K. Oberlaender, and M. Goessel, "New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability," in Proceeding of the 14th IEEE International Online Testing Symposium, Rhodes, Greece, pp. 37-42, 2008.
  8. R. Datta and N. A. Touba, "Exploiting Unused Spare Columns to Improve Memory ECC," in Proceeding of the 27th IEEE VLSI Test Symposium, Santa Cruz: CA, USA, pp. 47-52, 2009.