• Journal of the Korean institute of surface engineering
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• v.35 no.6
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.865-869
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• 2002

We investigated the reaction stability of titanium, cobalt and their bilayer films with side-wall spacer materials of SiO$_2$ for the salicide process. We prepared Ti 350 $\AA$, Co 150 $\AA$, Co 150 $\AA$/Ti 100 $\AA$ and Ti 100 $\AA$/Co 150 $\AA$ films on 1000 $\AA$-thick thermally grown SiO$_2$ substrates, respectively. Then the samples were rapid thermal annealed at the temperatures of $500^{\circ}C$, $600^{\circ}C$, and $700^{\circ}C$ for 20 seconds. We characterized the sheet resistance of the metallic layers with a four-point probe, surface roughness with scanning probe microscope, residual phases with an Auger depth profilometer, phase identification with a X-ray diffractometer, and cross-sectional microstructure evolution with a transmission electron microscope, respectively. We report that Ti reacted with silicon dioxide spacers above $700^{\circ}C$, Co agglomerated at $600^{\circ}C$, and Co/Ti, Ti/Co formed CoTi compound requiring a special wet process.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• Korean Journal of Materials Research
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• v.13 no.2
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• pp.88-93
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• 2003

Co/Ti bilayer structure in Co salicide process helps to the improvement of device speed by lowering contact resistance due to the epitaxial growth of $CoSi_2$layers. We investigated the epitaxial growth and interfacial mass transport of $CoSi_2$layers formed from $150 \AA$-Co/Ti structure with two step rapid thermal annealing (RTA). The thicknesses of Ti layers were varied from 20 $\AA$ to 100 $\AA$. After we confirmed the appropriate deposition of Ti film even below $100\AA$-thick, we investigated the cross sectional microstructure, surface roughness, eptiaxial growth, and mass transportation of$ CoSi_2$films formed from various Ti thickness with a cross sectional transmission electron microscopy XTEM), scanning probe microscopy (SPM), X-ray diffractometery (XRD), and Auger electron depth profiling, respectively. We found that all Ti interlayer led to$ CoSi_2$epitaxial growth, while $20 \AA$-thick Ti caused imperfect epitaxy. Ti interlayer also caused Co-Ti-Si compounds on top of $CoSi_2$, which were very hard to remove selectively. Our result implied that we need to employ appropriate Ti thickness to enhance the epitaxial growth as well as to lessen Co-Ti-Si compound formation.

• Korean Journal of Materials Research
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• v.13 no.5
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• pp.279-284
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• 2003

The $CoSi_2$ process is widely employed in a salicide as well as an ohmic layer process. In this experiment, we investigated the characteristics of $CoSi_2$ films by combinations of I-type (TiN 100$\AA$/Co 150$\AA$), II-type(TiN 100$\AA$/Co 150$\AA$/Ti 50$\AA$), III-type(Ti 100$\AA$/Co 150$\AA$/Ti 50$\AA$), and IV-type(Ti 100$\AA$/Co 150$\AA$/Ti 100$\AA$). Sheet resistances of $CoSi_2$ show the lowest resistance with 2.9 $\Omega$/sq. in a TiN/Co condition and much higher resistances in conditions simultaneously applying Ti capping layers and Ti interlayers. Though we couldn't observe a $CoSi_2$roughness dependence on the film stacks from RMS values, Ti capping layers turned into 78∼94$\AA$ thick TiN layers of (200) preferred orientation at $N_2$ambient. In addition, Ti interlayers helped to form the epitaxial $CoSi_2$with (200) preferred orientation and ternary compounds of Co-Ti-Si. We propose that film structures of II-type and III-type may be appropriate in the salicide process and the ohmic layer process from the viewpoint of Co diffusion kinetics and the CoSi$_2$epitaxy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.308-317
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/(poly)Si and 10 nm-$Ni_{0.5}Co_{0.5}$/(Poly)Si structures to investigate the microstructure of nickel silicides at the elevated temperatures required lot annealing. Silicides underwent rapid annealing at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profilescope were employed for the determination of vortical microstructure and thickness. Nickel silicides with cobalt on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1100^{\circ}C$ and $900^{\circ}C$, respectively, while the conventional nickle monosilicide showed low resistance below $700^{\circ}C$. Through TEM analysis, we confirmed that a uniform, $10{\sim}15 nm$-thick silicide layer formed on the single-crystal silicon substrate for the Co-alloyed case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo-alloy composite silicide process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.671-674
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• 2003

본 논문에서는 Cobalt interlayer 와 Titanium Nitride(TiN) capping layer를 Ni SALICIDE의 단점인 열 안정성과 sheet resistance 와 series 저항을 감소시키는데 적용하여 0.lum 급 CMOS 소자의 특성을 연구하였다. 첫째로, Ni/Si 의 interface 에 Co interlayer 를 증착하여 Nickel Silicide의 단점인 열 안정성 평가인 700℃, 30min의 furnace annealing 후에 낮은 sheet resistance와 누설전류를 줄일 수 있었다. 두번째로, TiN caping layer를 적용하여 실리사이드 형성시 산소와의 반응을 막아 실리사이드의 표면특성을 향상시켜 누설전류의 특성을 개선하였다. 결과적으로 소자의 구동전류 향상, 누설전류 저하, 낮은 면저항으로 소자의 특성을 개선하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.195-200
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/70 w-Poly-Si/200 $nm-SiO_2/Si$ and $10nm-Ni_{0.5}Co_{0.5}/70$ nm-Poly-Si/200 $nm-SiO_2/Si$ structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required fur annealing. Silicides underwent rapid anneal at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of the polycrystalline silicon substrate mimicking the gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profile scope were employed for the determination of cross sectional microstructure and thickness. 20nm thick nickel cobalt composite silicides on polycrystalline silicon showed low resistance up to $900^{\circ}C$, while the conventional nickle silicide showed low resistance below $900^{\circ}C$. Through TEM analysis, we confirmed that the 70nm-thick nickel cobalt composite silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. We identified $Ni_3Si_2,\;CoSi_2$ phase at $700^{\circ}C$ using an X-ray diffractometer. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo composite silicide from NiCo alloy films process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.