• 한국재료학회지
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• 제14권12호
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• pp.846-850
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• 2004

NiCo silicide films have been fabricated from $300{\AA}-thick\;Ni_{1-x}Co_{x}(x=0.1\sim0.9)$ on Si-substrates by varying RTA(rapid thermal annealing) temperatures from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 sec. Sheet resistance, cross-sectional microstructure, and chemical composition evolution were measured by a four point probe, a transmission electron microscope(TEM), and an Auger depth profilemeter, respectively. For silicides of the all composition and temperatures except for $80\%$ of the Ni composition, we observed small sheet resistance of sub- $7\;{\Omega}/sq.,$ which was stable even at $1100^{\circ}C$. We report that our newly proposed NiCo silicides may obtain sub 50 nm-thick films by tunning the nickel composition and silicidation temperature. New NiCo silicides from NiCo-alloys may be more appropriate for sub-0.1${\mu}m$ CMOS process, compared to conventional single phase or stacked composit silicides.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.149-154
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• 2005

궁극적으로 게이트를 저저항 복합 실리사이드로 대체하는 가능성을 확인하기 위해 70 nm 두께의 폴리실리콘 위에 각 20nm의 Ni, Co를 열증착기로 적층순서를 달리하여 poly/Ni/Co, poly/Co/Ni구조를 만들었다. 쾌속열처리기를 이용하여 실리사이드화 열처리를 40초간 $700{\~}1100^{\circ}C$ 범위에서 실시하였다. 복합 실리사이드의 온도별 전기저항변화, 두께변화, 표면조도변화를 각각 사점전기저항측정기와 광발산주사전자현미경, 주사탐침현미경으로 확인하였다. 적층순서와 관계없이 폴리실리콘으로부터 제조된 복합실리사이드는 $800^{\circ}C$ 이상부터 급격한 고저항을 보이고, 두께도 급격히 얇아졌다. 두께의 감소는 기존의 단결정에서는 없던 현상으로 폴리실리콘의 두께가 한정된 경우 금속성분의 inversion 현상이 커서 폴리실리콘이 오히려 실리사이드 상부에 위치하여 제거되기 때문이라고 생각되었고 $1000^{\circ}C$ 이상에서는 실리사이드가 형성되지 못하였다. 이러한 결과는 나노급 두께의 게이트를 저저항 실리사이드로 만 들기 위해서는 inversion과 두께감소를 고려하여야 함을 의미하였다.

• Transactions on Electrical and Electronic Materials
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• 제9권4호
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• pp.137-142
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• 2008

The parasitic resistance is studied to silicon/metal contact junction for improving device performance and to lower contact/serial resistance silicide in natural sequence. In this paper constructs the stepwise Ni silicide process for parasitic resistance reduction for silicon/metal contact junction. We have investigated multi-step Ni silicide on SiGe substrate with stepwise annealing method as an alternative to compose more thermally reliable Ni silicide layer. Stepwise annealing for silicide formation is exposed to heating environment with $5^{\circ}C/sec$ for 10 seconds and a dwelling for both 10 and 30 seconds, and ramping-up and the dwelling was repeated until the final annealing temperature of $700\;^{\circ}C$ is achieved. Finally a direct comparison for single step and stepwise annealing process is obtained for 20 nm nickel silicide through stepwise annealing is $5.64\;{\Omega}/square$ at $600\;^{\circ}C$, and it is 42 % lower than that of as nickel sputtered. The proposed stepwise annealing for Ni silicidation can provide the least amount of NiSi at the interface of nickel silicide and silicon, and it provides lower resistance, higher thermal-stability, and superior morphology than other thermal treatment.

• 한국전기전자재료학회논문지
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• 제20권4호
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• pp.308-317
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/(poly)Si and 10 nm-$Ni_{0.5}Co_{0.5}$/(Poly)Si structures to investigate the microstructure of nickel silicides at the elevated temperatures required lot annealing. Silicides underwent rapid annealing at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profilescope were employed for the determination of vortical microstructure and thickness. Nickel silicides with cobalt on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1100^{\circ}C$ and $900^{\circ}C$, respectively, while the conventional nickle monosilicide showed low resistance below $700^{\circ}C$. Through TEM analysis, we confirmed that a uniform, $10{\sim}15 nm$-thick silicide layer formed on the single-crystal silicon substrate for the Co-alloyed case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo-alloy composite silicide process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• 대한금속재료학회지
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• 제46권2호
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• pp.88-96
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• 2008

Thermal evaporated 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films were deposited to examine the energy saving properties of silicides formed by rapid thermal annealing at temperature ranging from 500 to $1,100^{\circ}C$ for 40 seconds. Thermal evaporated 10 nm-Ni/(70 nm-poly)Si films were also deposited as a reference using the same method for depositing the 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films. A four-point probe was used to examine the sheet resistance. Transmission electron microscopy (TEM) and X-ray diffraction XRD were used to determine cross sectional microstructure and phase changes, respectively. UV-VIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were used to examine the near-infrared (NIR) and middle-infrared (MIR) absorbance. TEM analysis confirmed that the uniform nickel-cobalt composite silicide layers approximately 21 to 55 nm in thickness had formed on the single and polycrystalline silicon substrates as well as on the 25 to 100 nm thick nickel silicide layers. In particular, nickel-cobalt composite silicides showed a low sheet resistance, even after rapid annealing at $1,100^{\circ}C$. Nickel-cobalt composite silicide and nickel silicide films on the single silicon substrates showed similar absorbance in the near-IR region, while those on the polycrystalline silicon substrates showed excellent absorbance until the 1,750 nm region. Silicides on polycrystalline substrates showed high absorbance in the middle IR region. Nickel-cobalt composite silicides on the poly-Si substrates annealed at $1,000^{\circ}C$ superior IR absorption on both NIR and MIR region. These results suggest that the newly proposed $Ni_{50}Co_{50}$ composite silicides may be suitable for applications of IR absorption coatings.

• 한국산학기술학회논문지
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• 제6권3호
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• pp.273-277
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• 2005

새로이 제안된 15nm-Ni/15nm-Co의 적층구조로부터 제조된 NiCo 복합실리사이드를 실제 디바이스에 채용하기 위해, $SiO_2$ 스페이서를 가진 폴리실리콘 게이트 선폭이 $0.25\~l.5um$까지 변화하는 테스트그룹을 이용하여 30초-RTA를 이용한 실리사이드화 온도를 $700^{\circ}C\~1100^{\circ}C$까지 변화시키면서 이때 cleaning전후의 잔류금속의 생성모습을 확인하였다. RTA온도가 올라갈수록 $SiO_2$로 구성된 필드와 스페이서 상부와, 실리사이드가 형성된 게이트 상부에 $0.25{\mu}m$정도의 단축직경을 가진 타원형 잔류금속이 미로형 또는 게이트 방향으로 생성되는 특징이 있었고 동시에 응집이 많아지는 현상이 있었다. 응집이 많을수록 하부 절연층과의 반응도가 증가하여 절연특성이 저하될 수 있었고 과도한 습식제거 공정을 오래하여야 하므로 실험범위 내에서 가급적 저온 실리사이드화 열처리가 바람직하였다.

• 한국재료학회지
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• 제17권2호
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.195-200
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• 2007

최소선폭 $0.1{\mu}m$ 이하의 살리사이드 공정을 상정하여 $10nm-Ni_{0.5}Co_{0.5}/70\;nm-Poly-Si/200\;nm-SiO_2$ 구조로부터 쾌속 열처리를 이용해서 실리사이드 온도를 $600{\sim}1100^{\circ}C$까지 변화시키면서 복합실리사이드를 제조하고 이들의 면저항의 변화와 미세구조의 변화를 면저항 측정기와 TEM 수직단면, 오제이 두께 분석으로 확인하였다. 기존의 동일한 공정으로 제조된 니켈실리사이드에 비해 제안된 니켈 코발트 복합실리사이드는 $900^{\circ}C$까지 저저항을 유지시킬 수 있는 장점이 있었고 20nm 두께의 균일한 실리사이드 층을 폴리실리콘 상부에 형성시킬 수 있었다. 고온 처리시에는 복합실리사이드와 실리콘의 전기적으로 상분리되는 혼합현상으로 고저항 특성이 나타나는 문제를 확인하였다. 제안된 NiCo 합금 박막을 70nm 높이의 폴리실리콘 게이트를 가진 디바이스에 $900^{\circ}C$이하의 실리사이드화 온도에서 효과적으로 산리사이드 공정의 적용이 기대되었다.

• Transactions on Electrical and Electronic Materials
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• 제9권2호
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• pp.47-51
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• 2008

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.667-670
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• 2003

Ni-silicide has low thermal stabiliy. This point is obstacle to apply NiSi to devices. So In this paper, we have studied for obtain thermal stability and analysis of dopant dependency of NiSi. And then we applied Ni-silicide to devices. To improvement of thermal stability, we deposit Ni70/Co10/Ni30/TiN100 to sample. Co midlayer is enhanced thermal stability of NiSi. Co/Ni/TiN, this structure show very difference between n-poly and p-poly in sheet resistance. But Ni/Co/Ni/TiN, structure show less difference. Also junction leakage is good.