• Journal of Positioning, Navigation, and Timing
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• v.4 no.1
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• pp.25-31
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• 2015

In this paper, we described the timing-offset comparison results between various daily jump compensation methods for GPS carrier phase (CP) measurement data. For the performance comparison, we used about 70 days GPS measurement data obtained from two GPS geodetic receivers which share the reference 1 PPS and RF signals and closely located in each other within a few meters. From the experiment results, the followings were observed. First, daily jumps existed in CP measurements depend on not only the environment but also the receiver which will make a full compensation be very hard or impossible. Second, clock bias can be occurred in the case of using a simple compensation with accumulation of daily jumps but it could be used in a short-period frequency comparison campaign (less than about 7 days) despite of its drawback.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1190-1196
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• 2014

This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2307-2314
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• 2015

This paper focuses on the generation algorithm of BeiDou pseudorange correction (PRC) and simulation based performance verification for design of Differential Global Navigation Satellite System (DGNSS) reference station and integrity monitor (RSIM) in order to prepare for recapitalization of DGNSS. First of all, it discusses the International standard on DGNSS RSIM, based on the interface control document (ICD) for BeiDou, estimates the satellite position using satellite clock offset and user receiver clock offset, and the system time offset between Global Positioning System (GPS) and BeiDou. Using the performance verification platform interfaced with GNSS (GPS/BeiDou) simulator, it calculates the BeiDou pseudorange corrections , compares the results of position accuracy with GPS/DGPS. As the test results, this paper verified to meet the performance of position accuracy for DGNSS RSIM operation required on Radio Technical Commission for Maritime Services (RTCM) standard.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.51-56
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• 2009

Time synchronization algorithm in wireless sensor networks is essential to various applications such as object tracking, data encryption, duplicate detection, and precise TDMA scheduling. This paper describes CDRS that is a time synchronization algorithm using the Clock Drift rate and Reference Signals between two sensor nodes. CDRS is composed of two steps. At first step, the time correction is calculated using offset and the clock drift rate between the two nodes based on the LTS method. Two nodes become a synchronized state and the time variance can be compensated by the clock drift rate. At second step, the synchronization node transmits reference signals periodically. This reference signals are used to calculate the time difference between nodes. When this value exceeds the maximum error tolerance, the first step is performed again for resynchronization. The simulation results on the performance analysis show that the time accuracy of the proposed algorithm is improved, and the energy consumption is reduced 2.5 times compared to the time synchronization algorithm with only LTS, because CDRS reduces the number of message about 50% compared to LTS and reference signals do not use the data space for timestamp.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.255-265
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• 2012

This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-nm CMOS process, demonstrating the measured results of 2-GHz frequency tuning range, -11.3-dBm output power, -109.6-dBc/Hz phase noise at 1-MHz offset, and 2-ps RMS clock jitter at 15 GHz. The chip core occupies the area of $0.2mm^2$ and dissipates 12 mW from a single 1.2-V supply.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.28-36
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• 1997

In this paper, system application techniques of a low-voltage low-power CMOS comparator are proposed. The proposed techniques employ poly-layer lines instead of conventional dummy cells to improve the accuracy of comparators which are located in both ends of a comparator array. This technique is easily applicable for hihg-density systems such as memory. The proposed circuits are implemented using a 0.6 um signle-poly double-metal n-well CMOS technology and the dissipated power is 0.38 mW. at a 20MHz clock speed based on a 3V supply. The comparator offsets are measured separately and compared for system applications. Using the proposed techniues, the measured comparator offsets are reduced by 40% of a conventional case.

• Korean Journal of Geomatics
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• v.4 no.2
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• pp.47-52
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• 2004

We can process and compute the position, velocity and time by satellite signals of GPS. The signals are used to compute positioning of three dimensions and timing offset of the receiver clock when we can track the tour satellite signals at least. One of the specified aims is to use less expensive single frequency code/carrier phase GPS receivers, which are typically around half the price of dual frequency receivers. In the study, the author analyzed the accuracy and applicability of frequence linear combination using triangulation points evaluated distance limitation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.971-981
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• 2009

The coordination of distributed entities and events requires time synchronization. Precision time synchronization enables a variety of extensions of applications and provides much accurate information. The IEEE 1588 precision time protocol (PTP) provides a standard method to synchronize devices in a network. This paper deals with the design and implementation of a PTP gateway to extend IEEE 1588 to Zigbee networks. The PTP gateway can not only extend IEEE 1588 to Zigbee networks but also share the same time reference using IEEE 1588 between two or more Zigbee networks. This paper also presents experiments and performance evaluation of time synchronization using the PTP gateway. Our result established a method for nodes in a network to maintain their clocks to within a 300 nanosecond offset from the reference clock of a master node via Ethernet.