• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.27-33
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• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.461-463
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• 2018

In this paper, we have studied the devices needed for long distance wireless transmission of SDH network. This devices propose wireless transmission and measurement method of STM-1(basic transmission unit of SDH method) signal and 200Mbps synchronous ethernet. The synchronous clock recovery function is provided for STM-N transmission and synchronous ethernet transmission, and spare clock switching function is designed for stable synchronization. In addition, we discussed the measurement method of STM-N and synchronous Etherent communication method in wireless transmission section.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.31-38
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• 2003

A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Journal of Life Science
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• v.25 no.11
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• pp.1304-1310
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• 2015

The period circadian clock gene 3 (PER3) plays a role in the mammalian circadian clocksystem. A regular exercise regime may affect the PER3 transcription in skeletal muscle. Although the effects of day length on circadian and circannual processes are well established in humans and mice, the influence of exercise on these processes in the horse has not been investigated. The present study investigated the expression of the PER3 gene following exercise in a thoroughbred breed of Korean horse. In addition, a comprehensive in silico nonsynonymous single nucleotide polymorphism (nsSNP) analysis of the horse PER3 gene and predicted effects of nsSNPs on proteins were examined. The expression of PER3 in skeletal muscle was significantly upregulated after exercise. Four nsSNPs were functionally annotated and analyzed by computational prediction. The total free energy and RMSD values of PER3 gene showed causative mutations. The results showed that nsSNP s395916798 (G72R) was associated with residues that have stabilizing effects on structure and function of PER3 gene. This study documented role of PER3 gene in phenotypic adaptation related to exercise in skeletal muscle. Further, the SNPs in PER3 could serve as useful biomarkers of early recovery after exercise in racehorses.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• ETRI Journal
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• v.35 no.3
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• pp.386-396
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• 2013

A 10-Gbit/s wireless communication system operating at a carrier frequency of 300 GHz is presented. The modulation scheme is amplitude shift keying in incoherent mode with a high intermediate frequency (IF) of 30 GHz and a bandwidth of 20 GHz for transmitting a 10-Gbit/s baseband (BB) data signal. A single sideband transmission is implemented using a waveguide-tapered 270-GHz high-pass filter with a lower sideband rejection of around 60 dB. This paper presents an all-electronic design of a terahertz communication system, including the major modules of the BB and IF band as well as the RF modules. The wireless link shows that, aided by a clock and data recovery circuit, it can receive $2^7$-1 pseudorandom binary sequence data without error at up to 10 Gbit/s for over 1.2 m using collimating lenses, where the transmitted power is 10 ${\mu}W$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.521-530
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• 1989

Broadband ATM(Asynchronous Transfer Mode) networking techniques based on lightwave technology and high speed integrated circuits appear to be the choice of transport technology for broadband ISDN. Among other problems, the issue of video transport over broadband packet(ATM) networks still requries further investigation. In this paper, the problems of transporting video signals over a broaband packet network are investigated together with possible solutions. In particular, clock recovery packet loss compensation and transport technique based on hierarchical video coding scheme are described in detail. This would allow efficient bandwidth sharing and minimum degradation in video quality.

• Journal of the Optical Society of Korea
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• v.20 no.4
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• pp.464-469
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• 2016

All-optical non-return-to-zero (NRZ) -to- return-to-zero (RZ) data-format conversion has been successfully demonstrated using a semiconductor optical amplifier in a fiber-loop mirror (so-called SOA-loop mirror) with a continuous-wave (CW) holding beam. The converted RZ signal after pulse compression has been used to create a 40 Gb/s OTDM (Optical Time Division Multiplexing) signal. Here is proposed an NRZ-to-RZ conversion method without any additional optical clocks, unlike conventional methods based on optical AND logic. In addition, it has the merit of operating at various bit-rate speeds without any controlling device. Moreover, it has a simple structure, and it can be used for all-optical bit-rate-flexible clock recovery.